07efd6f1e0
When inserting new instructions, use getFirstInsertionPt instead of
...
getFirstNonPHI so that it will skip over the landingpad instructions as well.
llvm-svn: 138537
2011-08-25 01:08:34 +00:00
f066b2fe99
Add a command line option to disable global merge pass.
...
llvm-svn: 138536
2011-08-25 01:00:36 +00:00
3ca20e64ac
Remove a out-of-place comment.
...
llvm-svn: 138534
2011-08-25 00:54:42 +00:00
50d74211df
Create a section for non-instructions patterns in the beginning of the
...
file, and move more code around!
llvm-svn: 138521
2011-08-24 23:18:11 +00:00
2fb51d38e6
Move code around!
...
llvm-svn: 138520
2011-08-24 23:18:09 +00:00
fb702fe8d6
Organize UNPCK* patterns, also add remaining for AVX.
...
llvm-svn: 138519
2011-08-24 23:18:06 +00:00
9ade17b7f2
Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate
...
the missing ones for AVX.
llvm-svn: 138518
2011-08-24 23:18:04 +00:00
c1e1e7ab97
Organize and tidy up MOVDDUP section. Also update comments!
...
llvm-svn: 138517
2011-08-24 23:18:02 +00:00
813891a215
Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the
...
pattern for 128-bit AVX mode.
llvm-svn: 138516
2011-08-24 23:17:59 +00:00
9566a66a7c
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!
llvm-svn: 138515
2011-08-24 23:17:57 +00:00
2953d7b320
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
llvm-svn: 138514
2011-08-24 23:17:55 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
9c73a57b20
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
...
llvm-svn: 138505
2011-08-24 22:33:28 +00:00
eee864520c
Some autoconf tests use module level inline asm to test compiler's handling of
...
.cfi_startproc. e.g. libffi:
$ cat confopt.c
asm (".cfi_startproc\n\t.cfi_endproc");
int main () { return 0; }
Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.
rdar://10017184
llvm-svn: 138504
2011-08-24 22:31:37 +00:00
b2a2c031b8
Update tests for 138501.
...
llvm-svn: 138502
2011-08-24 22:30:18 +00:00
21a60b6f90
ARM asm backend initialize isThumbMode based on target triple.
...
llvm-svn: 138501
2011-08-24 22:27:35 +00:00
838ed3af46
Thumb .n mnemonic qualifiers can be ignored for now.
...
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
...
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
38cd821dc4
Fix whitespace.
...
llvm-svn: 138487
2011-08-24 21:17:30 +00:00
5aabaaa367
Basic tests for atomic load and store on x86.
...
llvm-svn: 138486
2011-08-24 21:16:59 +00:00
86c5cbe613
Skip the landingpad instruction when determining the insertion point.
...
llvm-svn: 138481
2011-08-24 21:06:46 +00:00
342e8df0e0
Basic x86 code generation for atomic load and store instructions.
...
llvm-svn: 138478
2011-08-24 20:50:09 +00:00
0902a68f69
Use getFirstInsertionPt instead of getFirstNonPHI so that it skips to the proper
...
insertion place.
llvm-svn: 138473
2011-08-24 20:28:43 +00:00
0cb3b56de5
Some minor updates to atomic acquire/release docs in LangRef.
...
llvm-svn: 138472
2011-08-24 20:28:39 +00:00
365af6f17b
Implement Constant::isAllOnesValue(). Fix ConstantFolding to use the new api.
...
llvm-svn: 138469
2011-08-24 20:18:38 +00:00
af2f827a2c
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
...
rdar://10015134
llvm-svn: 138467
2011-08-24 20:06:14 +00:00
ce02840633
Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138461
2011-08-24 18:48:33 +00:00
6ccd79f4d5
Add missing explicit writeback operand to tSTMIA_UPD.
...
rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
d3e65e702f
Fix a crashing bug in SplitBlock when it is called on a block with no
...
dominator information even though dominators were previously computed.
Patch by Nick Sumner.
llvm-svn: 138449
2011-08-24 18:07:01 +00:00
a281f2d07d
Thumb add SP assembly syntax fix.
...
llvm-svn: 138448
2011-08-24 18:04:27 +00:00
1b8457a84c
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
...
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
16fd0d96f2
Port over more encoding tests to decoding tests.
...
llvm-svn: 138441
2011-08-24 17:08:34 +00:00
dee9e8a37c
Tidy up. Trailing whitespace.
...
llvm-svn: 138437
2011-08-24 16:44:17 +00:00
6e3c83eb1c
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
...
variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
de92622aa5
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
...
llvm-svn: 138427
2011-08-24 06:14:18 +00:00
f4ee0c0db2
Add the sentinal "no handle" value to the ResumeInst.
...
A value of -1 at a call site tells the personality function that this call isn't
handled by the current function. Since the ResumeInsts are converted to calls to
_Unwind_SjLj_Resume, add a (volatile) store of -1 to its 'call site'.
llvm-svn: 138416
2011-08-24 00:00:23 +00:00
2d4f0bea57
Don't replace *all* uses with the new stuff.
...
This is not necessarily the first or dominating use of the EH values. The IR
breaks if it's not. So replace the specific value in the instruction with the
new value.
llvm-svn: 138406
2011-08-23 22:55:03 +00:00
01a325a40e
Look at the end of the entry block for an invoke.
...
The invoke could be at the end of the entry block. If it's the only one, then we
won't process all of the landingpad instructions correctly. This code is
currently ugly, but should be made much nicer once the new EH switch is thrown.
llvm-svn: 138397
2011-08-23 22:20:16 +00:00
9e9f2ce32d
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
...
permutations. Also tidy up some patterns and make them close to their
instruction definition!
llvm-svn: 138392
2011-08-23 22:06:37 +00:00
4eb0433672
A landingpad instruction is neither folded nor dead.
...
llvm-svn: 138387
2011-08-23 21:33:05 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
...
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
50b0f6669c
[SU]XT[BH] are only available on ARMv6 and up.
...
llvm-svn: 138373
2011-08-23 20:53:08 +00:00
43c322b5b2
Add some useful accessors to c++ api that appear to be missing from the c api
...
llvm-svn: 138371
2011-08-23 20:27:46 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
...
from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
7bc78f692c
Revert "Address Duncan's CR request:"
...
This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340)
Conflicts:
test/Transforms/InstCombine/bitcast.ll
llvm-svn: 138366
2011-08-23 20:11:10 +00:00
37563cd545
Thumb parsing and encoding for WFE, WFI and YIELD.
...
llvm-svn: 138364
2011-08-23 20:02:30 +00:00
ad9e8655ee
Thumb parsing and encoding for UXTB and UXTH.
...
llvm-svn: 138363
2011-08-23 19:59:32 +00:00
5e4ea175f6
Thumb parsing and encoding for TST.
...
llvm-svn: 138362
2011-08-23 19:53:17 +00:00
bb07e73e0d
Thumb parsing and encoding for SXTB and SXTH.
...
llvm-svn: 138361
2011-08-23 19:51:42 +00:00
5cc338da67
Thumb parsing and encoding for SVC.
...
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
d88404fbaa
Thumb parsing and encoding for SUB.
...
llvm-svn: 138359
2011-08-23 19:45:45 +00:00
6b477b985b
Fix 80 col violations.
...
llvm-svn: 138356
2011-08-23 19:17:21 +00:00
4c8ff77f1b
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
...
llvm-svn: 138354
2011-08-23 19:01:24 +00:00
f1ca6a6df6
Thumb parsing and encoding for STRH.
...
llvm-svn: 138352
2011-08-23 18:56:20 +00:00
ffa5a909b4
Thread safety: Adding in an option for variadic expr* array of arguments
...
llvm-svn: 138351
2011-08-23 18:49:23 +00:00
635aa69a91
Thumb parsing and encoding for STRB.
...
llvm-svn: 138349
2011-08-23 18:43:06 +00:00
505be75900
Thumb parsing and encoding for tSTRspi.
...
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
6e546e0725
Thumb parsing and encoding for STR.
...
Not including tSTRspi.
llvm-svn: 138347
2011-08-23 18:33:38 +00:00
f9a688176f
Fix an example in the documentation.
...
Patch by Sanjoy Das!
llvm-svn: 138346
2011-08-23 18:26:56 +00:00
d80d169a04
Thumb parsing and encoding for STM.
...
llvm-svn: 138345
2011-08-23 18:15:37 +00:00
169b2be611
Factor low reg checking into a helper function.
...
llvm-svn: 138344
2011-08-23 18:13:04 +00:00
7d3effa389
Fix a typo in the test from the previous commit.
...
llvm-svn: 138342
2011-08-23 17:56:54 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
c78e6607b5
Address Duncan's CR request:
...
1. Cleanup the tests in ConstantFolding.cpp
2. Implement isAllOnes for Constant, ConstantFP, ConstantVector
llvm-svn: 138340
2011-08-23 17:48:43 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
...
llvm-svn: 138339
2011-08-23 17:45:18 +00:00
e364ad540a
Clean up Thumb load/store multiple definitions.
...
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
llvm-svn: 138338
2011-08-23 17:41:15 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
...
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
dcea63236e
Port more assemble tests over to disassembly tests.
...
llvm-svn: 138336
2011-08-23 17:26:35 +00:00
771ef8c66a
This patch adds support of le32 pseudo-cpu that stands for generic
...
32-bit little-endian CPU. Used by PNaCl and Emscripten.
llvm-svn: 138335
2011-08-23 16:59:00 +00:00
c50ea3beaf
Fix fpimmm->fpimm typo.
...
Patch by Micah Villmow!
llvm-svn: 138330
2011-08-23 15:42:35 +00:00
05e609331c
Update config.sub, config.guess and configure.
...
The motivation to do that:
1. Now, llvm would use the stock config.sub. Before that we had an
uncommitted FreeBSD-related patch. Now, it has been upstreamed and
comes back. It means that it would be easier to update these files in
the next time (less magic knowledge)
2. Fix a typo for pseudo-CPUs: 32e[lb] -> [lb]e32, 64e[lb]->[lb]64.
One of these CPUs is used for PNaCl and it was not really convenient
to have a CPU that starts with a digit.
llvm-svn: 138323
2011-08-23 06:43:49 +00:00
6612e35b0d
Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.
...
llvm-svn: 138321
2011-08-23 04:36:33 +00:00
fd6cb64c48
lib/Support/Windows/Windows.h: Update required IE ver. 0x0600 should be enough for Windows XP.
...
llvm-svn: 138319
2011-08-23 03:49:11 +00:00
2a3ffb5d97
Introduce a pass to insert vzeroupper instructions to avoid AVX to
...
SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.
llvm-svn: 138317
2011-08-23 01:14:17 +00:00
cc9d792ec1
Thumb parsing and encoding for SETEND.
...
llvm-svn: 138312
2011-08-22 23:58:02 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
...
llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
...
llvm-svn: 138308
2011-08-22 23:47:13 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
...
llvm-svn: 138306
2011-08-22 23:44:04 +00:00
08b5c19a4d
Add an MCInstrAnalysis version of isCall.
...
llvm-svn: 138305
2011-08-22 23:41:41 +00:00
73661b8a37
Thumb parsing and encoding for ROR.
...
llvm-svn: 138304
2011-08-22 23:40:51 +00:00
a9d88df987
Thumb parsing and encoding for REV/REV16/REVSH.
...
llvm-svn: 138303
2011-08-22 23:39:25 +00:00
f0d2dfde4f
Split the landing pad's edge. Then for all uses of a landingpad instruction's
...
value, we insert a load of the exception object and selector object from memory,
which is where it actually resides. If it's used by a PHI node, we follow that
to where it is being used. Eventually, all landingpad instructions should have
no uses. Any PHI nodes that were associated with those landingpads should be
removed.
llvm-svn: 138302
2011-08-22 23:38:40 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
...
llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
...
llvm-svn: 138300
2011-08-22 23:27:47 +00:00
bfeb4f78af
Revert r138278 now that r138289 has fixed the root issue.
...
llvm-svn: 138299
2011-08-22 23:25:48 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
...
llvm-svn: 138298
2011-08-22 23:22:05 +00:00
2b462b54b9
docs/ReleaseNotes.html: Mention that Windows 2000 will not be supported any more.
...
llvm-svn: 138297
2011-08-22 23:22:05 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
...
llvm-svn: 138295
2011-08-22 23:17:34 +00:00
2844a81079
Match operand names to provide correct decoding for Thumb2 SMULL.
...
llvm-svn: 138294
2011-08-22 23:16:48 +00:00
096423b6be
Tidy up. Trailing whitespace.
...
llvm-svn: 138293
2011-08-22 23:13:54 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
...
llvm-svn: 138292
2011-08-22 23:10:16 +00:00
b296790bb6
Add NativeClient support to Triple::ParseOS.
...
llvm-svn: 138291
2011-08-22 23:08:53 +00:00
40da063178
Thumb parsing and encoding for PUSH.
...
llvm-svn: 138290
2011-08-22 23:05:11 +00:00
6aa2744bed
Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-)
...
llvm-svn: 138289
2011-08-22 23:04:56 +00:00
5507203262
Fix think-o.
...
llvm-svn: 138288
2011-08-22 23:04:26 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
...
llvm-svn: 138287
2011-08-22 23:01:07 +00:00
Bill Wendling