6c70e58041
Correct encoding of BL with immediate offset.
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llvm-svn: 138673
2011-08-26 22:54:51 +00:00
b9d4e37776
ARM assembly parsing tweak for pldw.
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llvm-svn: 138669
2011-08-26 22:21:51 +00:00
240d20af79
Spelling fail.
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llvm-svn: 138667
2011-08-26 21:47:57 +00:00
3d1eac85c3
Thumb2 assembler parsing and encoding of IT instruction.
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This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
llvm-svn: 138665
2011-08-26 21:43:41 +00:00
71fce2c84d
Update the dominator tree with the correct dominator for the new 'unwind' block.
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llvm-svn: 138664
2011-08-26 21:36:12 +00:00
5e5704277f
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
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llvm-svn: 138660
2011-08-26 21:21:21 +00:00
fee8eda35b
Split the landing pad block only if it's a critical edge. Also intelligently
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split it in the other place where we're splitting critical edges.
llvm-svn: 138658
2011-08-26 21:18:55 +00:00
fd60f60ed1
Fix ARM codegen breakage caused by r138653.
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llvm-svn: 138657
2011-08-26 21:12:37 +00:00
ac88ab7cce
Revert r138606 until LowerInvoke has been converted to the new EH scheme.
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llvm-svn: 138656
2011-08-26 21:11:23 +00:00
3cc90fe5a5
Whitespace and 80-col.
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llvm-svn: 138654
2011-08-26 21:02:40 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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llvm-svn: 138653
2011-08-26 20:43:14 +00:00
28dc5abd05
valgrind: Always suppress tblgen leaks.
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I'll clean up the rest of the XFAIL: vg_leak lines if this works.
llvm-svn: 138652
2011-08-26 20:41:20 +00:00
eed1e8905a
Don't sink landingpad instructions during ind-var simplification.
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llvm-svn: 138651
2011-08-26 20:40:15 +00:00
07aeb629ec
Use %% for literals in RUN lines.
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llvm-svn: 138647
2011-08-26 20:09:48 +00:00
5658b49f64
Update for feedback from Jim.
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llvm-svn: 138642
2011-08-26 19:39:26 +00:00
37e94d06ba
lit: Add %T as a replacement for the output directory
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llvm-svn: 138640
2011-08-26 19:05:18 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
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This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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llvm-svn: 138635
2011-08-26 18:09:22 +00:00
6eb9666bb8
We don't care if TableGen leaks memory.
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llvm-svn: 138634
2011-08-26 17:00:30 +00:00
db6f646ec3
Don't insert branch hint lables that are never used.
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llvm-svn: 138630
2011-08-26 10:14:56 +00:00
f3b6507e26
Add a testcase for r138625.
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llvm-svn: 138626
2011-08-26 06:45:08 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
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This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
c66d50d1a2
Fix disassembling of VCVTSD2SI
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llvm-svn: 138623
2011-08-26 04:49:29 +00:00
147d9cde78
LoopInfo::updateUnloop fix, and verify Block->Loop maps.
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Fixes an oversight, and adds verification to catch it in the unloop.ll tests.
llvm-svn: 138622
2011-08-26 03:06:34 +00:00
452aae6202
Atomic load/store on ARM/Thumb.
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I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
0655b78ccc
Address review comments.
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- Reword comments.
- Allow undefined behavior interfering with undefined behavior.
- Add address space checks.
llvm-svn: 138619
2011-08-26 02:25:55 +00:00
fb212a6309
SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between.
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In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.
This shrinks the size of a Release clang by 16k on x86_64.
llvm-svn: 138618
2011-08-26 01:22:29 +00:00
62fe9e9aa6
Update to the new EH scheme.
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llvm-svn: 138606
2011-08-25 23:48:37 +00:00
8ac2041a19
Look at only the terminators of the basic block. Also, if we're using the new EH
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scheme, return 'true' so that it doesn't try to run the old EH scheme's fixup on
the new code.
llvm-svn: 138605
2011-08-25 23:48:11 +00:00
45449b1cba
Initial check in that will auto-upgrade the old EH scheme to the new EH scheme.
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This upgrade suffers from the problems of the old EH scheme - i.e., that the
calls to llvm.eh.exception() and llvm.eh.selector() can wander off and get
lost. It makes a valiant effort to reclaim these little lost lambs.
This is a first draft, so it hasn't yet been hooked up to the parser.
llvm-svn: 138602
2011-08-25 23:22:40 +00:00
ed834810be
Do the same as r138461. Mark VZEROALL as clobbering all YMM registers
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llvm-svn: 138592
2011-08-25 22:23:58 +00:00
64bfca1b60
Remove stray fullstop.
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llvm-svn: 138589
2011-08-25 21:46:20 +00:00
8347b86293
Add support for AVX 256-bit version of MOVDDUP!
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llvm-svn: 138588
2011-08-25 21:40:37 +00:00
388eacee2c
Make isMOVDDUP mask check more strict and update comments!
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llvm-svn: 138587
2011-08-25 21:40:34 +00:00
6e913571a2
Constify Comparison
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Make ConstantInt::uge() const so it may be used in const contexts.
llvm-svn: 138579
2011-08-25 20:18:22 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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llvm-svn: 138575
2011-08-25 18:30:18 +00:00
5a122f37fe
Intel family 6 model 44 is Gulftown/Westmere-EP and doesn't have AVX.
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llvm-svn: 138573
2011-08-25 18:05:56 +00:00
6446bf780a
ARM fix for missing implicit operands on ldmia_ret.
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rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
f7ecc16c96
whitespace
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llvm-svn: 138566
2011-08-25 17:40:54 +00:00
1c171b121a
Explicitly disallow predication in Thumb1 assembly.
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llvm-svn: 138562
2011-08-25 17:23:55 +00:00
14380ff9a0
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
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llvm-svn: 138553
2011-08-25 08:11:01 +00:00
76e3e0b554
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
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llvm-svn: 138552
2011-08-25 07:42:00 +00:00
e1541838f9
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
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llvm-svn: 138551
2011-08-25 06:57:46 +00:00
3fb137f7ef
LSR wants to split the landing pad's critical edge. Let it do it, but use the
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proper function to do it.
llvm-svn: 138550
2011-08-25 05:55:40 +00:00
88e6d5945f
Initialize member variable.
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llvm-svn: 138548
2011-08-25 04:04:18 +00:00
296256fb32
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
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llvm-svn: 138546
2011-08-25 02:58:26 +00:00
54366cc332
Add memory version of SHUFPD to mask decoding!
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llvm-svn: 138545
2011-08-25 02:58:21 +00:00
ff2091737e
Update tests to the newest EH syntax.
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llvm-svn: 138541
2011-08-25 01:30:18 +00:00
9dad430486
Hide -global-merge option.
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llvm-svn: 138540
2011-08-25 01:22:49 +00:00
b37db20e40
Add feature test for the new exception handling stuff.
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llvm-svn: 138539
2011-08-25 01:19:13 +00:00
Owen Anderson