Commit Graph

1753 Commits

Author SHA1 Message Date
Krzysztof Parzyszek ac01994db9 [Hexagon] Fix a bug in r308502: post-inc offset is always 0
llvm-svn: 308510
2017-07-19 19:17:32 +00:00
Krzysztof Parzyszek 3fce9d9c49 [Hexagon] Handle subregisters in areMemAccessesTriviallyDisjoint
llvm-svn: 308502
2017-07-19 18:03:46 +00:00
Krzysztof Parzyszek b449dc189a [Hexagon] Handle subregisters and non-immediates in getBaseAndOffset
llvm-svn: 308485
2017-07-19 15:39:28 +00:00
Sumanth Gundapaneni d5aa0f3464 [Hexagon] Emit lookup tables in text section based on a flag
The flag "-hexagon-emit-lut-text" (defaulted to false) is added to decide
on where to keep the switch generated lookup table.
Differential Revision: https://reviews.llvm.org/D34818

llvm-svn: 308316
2017-07-18 15:31:37 +00:00
Krzysztof Parzyszek 5eef92eb7f [Hexagon] Remove custom lowering of loads of v4i16
The target-independent lowering works fine, except concatenating 32-bit
words. Add a pattern to generate A2_combinew instead of 64-bit asl/or.

llvm-svn: 308186
2017-07-17 15:45:45 +00:00
Krzysztof Parzyszek 302a9d41c6 [Hexagon] Replace ISD opcode VPACK with VPACKE/VPACKO, NFC
This breaks up pack-even and pack-odd into two separate operations.

llvm-svn: 308049
2017-07-14 19:02:32 +00:00
Krzysztof Parzyszek 9c084fc55d [Hexagon] Add intrinsics for data cache operations
This is the LLVM part, adding definitions for
  void @llvm.hexagon.Y2.dccleana(i8*)
  void @llvm.hexagon.Y2.dccleaninva(i8*)
  void @llvm.hexagon.Y2.dcinva(i8*)
  void @llvm.hexagon.Y2.dczeroa(i8*)
  void @llvm.hexagon.Y4.l2fetch(i8*, i32)
  void @llvm.hexagon.Y5.l2fetch(i8*, i64)
The clang part will follow.

llvm-svn: 308032
2017-07-14 15:58:48 +00:00
Jakub Kuderski 34327d28fd [NFC] Move DEBUG_TYPE below includes in Hexagon
llvm-svn: 307947
2017-07-13 20:26:45 +00:00
Krzysztof Parzyszek 89b2d7c938 [Hexagon] Use VSPLAT instead of COMBINE for vectors of type v2i32, NFC
This cleans up the vector shift patterns.

llvm-svn: 307935
2017-07-13 18:17:58 +00:00
Rafael Espindola 1beb702ba2 Fully fix the movw/movt addend.
The issue is not if the value is pcrel. It is whether we have a
relocation or not.

If we have a relocation, the static linker will select the upper
bits. If we don't have a relocation, we have to do it.

llvm-svn: 307730
2017-07-11 23:18:25 +00:00
Evandro Menezes 0cd23f5642 [CodeGen] Rename DEBUG_TYPE to match passnames
Rename missing DEBUG_TYPE "machine-scheduler" from backend files, which were
absent from https://reviews.llvm.org/rL303921.

Differential revision: https://reviews.llvm.org/D35231

llvm-svn: 307719
2017-07-11 22:08:28 +00:00
Krzysztof Parzyszek f67cd8259d [Hexagon] Do not rely on callee-saved info in hasFP
llvm-svn: 307675
2017-07-11 17:11:54 +00:00
Krzysztof Parzyszek c86e2ef3f5 [Hexagon] Add support for nontemporal loads and stores on HVX
Patch by Michael Wu.

Differential Revision: https://reviews.llvm.org/D35104

llvm-svn: 307671
2017-07-11 16:39:33 +00:00
Krzysztof Parzyszek f85dd9f4e5 [Hexagon] Convert typed ISD opcodes to generic ones, NFC
llvm-svn: 307582
2017-07-10 20:16:44 +00:00
Krzysztof Parzyszek 40df124eda [Hexagon] Remove unused ISD opcodes, NFC
llvm-svn: 307580
2017-07-10 20:13:44 +00:00
Krzysztof Parzyszek df4a05d6fb [Hexagon] Fix check for HMOTF_ConstExtend operand flag
This fixes https://llvm.org/PR33718.

llvm-svn: 307566
2017-07-10 18:38:52 +00:00
Krzysztof Parzyszek 0ac065f318 [Hexagon] Handle Hexagon-specific machine operand target flags in MIR
llvm-svn: 307564
2017-07-10 18:31:02 +00:00
Simon Pilgrim cb07d67a5c Fix some more -Wimplicit-fallthrough warnings. NFCI.
llvm-svn: 307411
2017-07-07 16:40:06 +00:00
Simon Pilgrim 087e87d595 [Hexagon] Fix some more -Wimplicit-fallthrough warnings. NFCI.
llvm-svn: 307395
2017-07-07 13:21:43 +00:00
Simon Pilgrim adb80fbaf4 [Hexagon] Fix -Wimplicit-fallthrough warnings. NFCI.
llvm-svn: 307374
2017-07-07 10:04:12 +00:00
Rafael Espindola 76287ab3a0 Rename and adjust processFixupValue.
It was not processing any value. All that it ever did was force
relocations, so name it shouldForceRelocation.

llvm-svn: 306906
2017-06-30 22:47:27 +00:00
Krzysztof Parzyszek 9eb75c4520 [Hexagon] Implement frame pointer elimination with -fomit-frame-pointer
It applies to leaf functions that are otherwise not required to have
a frame pointer.

llvm-svn: 306888
2017-06-30 21:21:40 +00:00
Sumanth Gundapaneni d2dd79bf84 [Hexagon] Guard the generation of lookup table
The llvm flag "-hexagon-emit-lookup-tables" guards the generation
of lookup table generated from a switch statement.
Differential Revision: https://reviews.llvm.org/D34819

llvm-svn: 306877
2017-06-30 20:54:24 +00:00
Sumanth Gundapaneni 8c5d59557d [Hexagon] Emit jump tables in text section based on a flag
This patch adds a new LLVM flag -hexagon-emit-jt-text which is defaulted to 
"false". The value "true" emits the switch generated jump tables in text section.
Differential Revision: https://reviews.llvm.org/D34820

llvm-svn: 306872
2017-06-30 20:21:48 +00:00
Sumanth Gundapaneni 19b74203b1 Revert "[Hexagon] Guard the generation of lookup table"
This reverts commit ae521f4192c3ed0202c047fec993cb59133dd1a0.
Wrong commit message

llvm-svn: 306871
2017-06-30 20:20:00 +00:00
Sumanth Gundapaneni cf73758dc8 [Hexagon] Guard the generation of lookup table
The llvm flag "-hexagon-emit-lookup-tables" guards the generation
of lookup table from a switch statement.

Differential Revision: https://reviews.llvm.org/D34819

llvm-svn: 306869
2017-06-30 20:10:28 +00:00
Krzysztof Parzyszek 0089419417 [Hexagon] Keep all phi nodes when building DFG in addr-mode-opt
The dead phis are needed for finding correct would-be reaching defs
in register propagation.

llvm-svn: 306690
2017-06-29 15:55:59 +00:00
Evgeny Astigeevich 70ed78e504 [TargetTransformInfo, API] Add a list of operands to TTI::getUserCost
The changes are a result of discussion of https://reviews.llvm.org/D33685.
It solves the following problem:

1. We can inform getGEPCost about simplified indices to help it with
   calculating the cost. But getGEPCost does not take into account the
   context which GEPs are used in.
2. We have getUserCost which can take the context into account but we cannot
   inform about simplified indices.

With the changes getUserCost will have access to additional information
as getGEPCost has.

The one parameter getUserCost is also provided.

Differential Revision: https://reviews.llvm.org/D34057

llvm-svn: 306674
2017-06-29 13:42:12 +00:00
Geoff Berry 66d9bdbca8 [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.
Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper

Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D34531

llvm-svn: 306554
2017-06-28 15:53:17 +00:00
Krzysztof Parzyszek 25173e4cba [Hexagon] Use proper predicate register state when expanding PS_vselect
llvm-svn: 306458
2017-06-27 19:59:46 +00:00
Krzysztof Parzyszek 5ddd2e5899 [Hexagon] Update kills in hexagon-nvj even more properly than before
Account for the fact that both, the feeder and the compare can be moved
over instructions that kill registers.

llvm-svn: 306443
2017-06-27 18:37:16 +00:00
Krzysztof Parzyszek 918e6d70bd [Hexagon] Handle cases when the aligned stack pointer is missing
llvm-svn: 306288
2017-06-26 14:17:58 +00:00
Rafael Espindola 6418856127 Simplify the processFixupValue interface. NFC.
llvm-svn: 306202
2017-06-24 05:22:28 +00:00
Rafael Espindola f351292141 Remove redundant argument.
llvm-svn: 306189
2017-06-24 00:26:57 +00:00
Rafael Espindola 801b42de31 ARM: move some logic from processFixupValue to applyFixup.
processFixupValue is called on every relaxation iteration. applyFixup
is only called once at the very end. applyFixup is then the correct
place to do last minute changes and value checks.

While here, do proper range checks again for fixup_arm_thumb_bl. We
used to do it, but dropped because of thumb2. We now do it again, but
use the thumb2 range.

llvm-svn: 306177
2017-06-23 22:52:36 +00:00
Krzysztof Parzyszek 717021772b Revert "[Hexagon] Handle decreasing of stack alignment in frame lowering"
This breaks passing of aligned function arguments.

llvm-svn: 306145
2017-06-23 19:47:04 +00:00
Krzysztof Parzyszek c0a102f505 [Hexagon] Remove call to printAndVerify from HexagonPassConfig
It causes an extra pass of the machine verifier to be added to the pass
manager, and causes test/CodeGen/Generic/llc-start-stop.ll to fail.

llvm-svn: 306140
2017-06-23 18:47:55 +00:00
Krzysztof Parzyszek bb2fcd1921 [Hexagon] Handle decreasing of stack alignment in frame lowering
llvm-svn: 306124
2017-06-23 16:53:59 +00:00
Krzysztof Parzyszek 9b7c1d2dcf [Hexagon] Properly update kill flags in HexagonNewValueJump
The feeder instruction will be moved to right before the compare, so
the updating code should not be looking for kills past the compare.

llvm-svn: 306059
2017-06-22 21:11:44 +00:00
Krzysztof Parzyszek 1a0da8d5a3 [Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux
Remove the previous, manual shuffling of the kill flags. 

llvm-svn: 306054
2017-06-22 20:43:02 +00:00
Krzysztof Parzyszek f63ad39e7d [Hexagon] Handle a global operand to A2_addi when creating duplexes
llvm-svn: 306012
2017-06-22 15:53:31 +00:00
Krzysztof Parzyszek 69ffba4595 [Hexagon] Recognize potential offset overflow for store-imm to stack
Reserve an extra scavenging stack slot if the offset field in store-
-immediate instructions may overflow.

llvm-svn: 306004
2017-06-22 14:11:23 +00:00
Rafael Espindola 88d9e37ec8 Use a MutableArrayRef. NFC.
llvm-svn: 305968
2017-06-21 23:06:53 +00:00
Krzysztof Parzyszek 5b933fee3c [Hexagon] Use MachineInstrBuilder instead of changing instruction in place
llvm-svn: 305953
2017-06-21 21:03:34 +00:00
Krzysztof Parzyszek fd048cc0ec [Hexagon] Handle more types of immediate operands in expand-condsets
llvm-svn: 305943
2017-06-21 19:21:30 +00:00
Eugene Zelenko 8361b0a9bb [Target] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 305757
2017-06-19 22:43:19 +00:00
Krzysztof Parzyszek 3a40b34123 [Hexagon] Don't kill live registers when creating mux out of tfr
The second part of r305300: when placing the mux at the later location,
make sure that it won't use any register that was killed between the
two original instructions. Remove any such kills and transfer them to
the mux.

llvm-svn: 305553
2017-06-16 12:24:03 +00:00
Krzysztof Parzyszek b3a8d20e27 [Hexagon] Generate store-immediate instructions for stack objects
Store-immediate instructions have a non-extendable offset. Since the
actual offset for a stack object is not known until much later, only
generate these stores when the stack size (at the time of instruction
selection) is small.

llvm-svn: 305305
2017-06-13 17:10:16 +00:00
Krzysztof Parzyszek c83c267b84 [Hexagon] Generate multiply-high instruction in isel
llvm-svn: 305302
2017-06-13 16:21:57 +00:00
Krzysztof Parzyszek de2ac17b7b [Hexagon] Don't kill live registers when creating mux out of tfr
When a mux instruction is created from a pair of complementary conditional
transfers, it can be placed at the location of either the earlier or the
later of the transfers. Since it will use the operands of the original
transfers, putting it in the earlier location may hoist a kill of a source
register that was originally further down. Make sure the kill flag is
removed if the register is still used afterwards.

llvm-svn: 305300
2017-06-13 16:07:36 +00:00
Krzysztof Parzyszek 9bd4d91037 [Hexagon] Stop pmpy recognition when shift conversion fails
The conversion of shifts from right shifts to left shifts may fail.
In such case, the pmpy recognition cannot proceed.

llvm-svn: 305289
2017-06-13 13:51:49 +00:00
Krzysztof Parzyszek 7aca2fd830 [Hexagon] Fixes and updates to the selection patterns
- Add some missing patterns.
- Use C4_cmplte in branch patterns.
- Fix signedness of immediate operand in M2_accii.

llvm-svn: 305085
2017-06-09 15:26:21 +00:00
Krzysztof Parzyszek 7881415510 [Hexagon] Add LLVM header to HexagonPatterns.td
llvm-svn: 305074
2017-06-09 13:30:58 +00:00
Krzysztof Parzyszek b1ada4e742 [Hexagon] Re-enable machine verifier after codegen passes
Remove "false" from the arguments to "addPass" in Hexagon's target pass
config.

llvm-svn: 305015
2017-06-08 21:25:36 +00:00
Krzysztof Parzyszek 8a7fb0fe51 [Hexagon] Skip mux generation when predicate register is undefined
llvm-svn: 305014
2017-06-08 20:56:36 +00:00
Nirav Dave 6a38cc6d67 [Hexagon] Speedup NumNodesBlocking calculation. NFCI.
llvm-svn: 305003
2017-06-08 18:49:25 +00:00
Krzysztof Parzyszek 5ba13825f0 [Hexagon] Generate 'inbounds' GEPs in HexagonCommonGEP
llvm-svn: 304937
2017-06-07 20:04:33 +00:00
Zachary Turner 264b5d9e88 Move Object format code to lib/BinaryFormat.
This creates a new library called BinaryFormat that has all of
the headers from llvm/Support containing structure and layout
definitions for various types of binary formats like dwarf, coff,
elf, etc as well as the code for identifying a file from its
magic.

Differential Revision: https://reviews.llvm.org/D33843

llvm-svn: 304864
2017-06-07 03:48:56 +00:00
Chandler Carruth 6bda14b313 Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.

I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.

This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.

Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).

llvm-svn: 304787
2017-06-06 11:49:48 +00:00
Mandeep Singh Grang 5e1697ef28 [llvm] Remove double semicolons
Reviewers: craig.topper, arsenm, mehdi_amini

Reviewed By: mehdi_amini

Subscribers: mehdi_amini, wdng, nhaehnle, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33924

llvm-svn: 304767
2017-06-06 05:08:36 +00:00
Krzysztof Parzyszek 066e8b56a0 [Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist
This allows using this function to test if an instruction can be converted
to a .new form.

llvm-svn: 304549
2017-06-02 14:07:06 +00:00
Krzysztof Parzyszek 3cf16576d5 [Hexagon] Fix dependence check in the packetizer
An incorrect check in the packetizer lead to an attempt to convert
an unconditional branch to a .new (conditional) form.

llvm-svn: 304442
2017-06-01 18:02:40 +00:00
Krzysztof Parzyszek 51fd5405d5 [Hexagon] Handle long-running simplification loop in idiom recognition
The initial assumption was that the simplification would converge to a
fixed point relatvely quickly. Turns out that there are legitimate situa-
tions where the complexity of the code causes it to take a large number
of iterations.

Two main changes:
- Instead of aborting upon hitting the limit, simply return nullptr.
- Reduce the limit to 10,000 from 100,000.

llvm-svn: 304441
2017-06-01 18:00:47 +00:00
Matthias Braun 5e394c3d6f TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFC
TargetPassConfig is not useful for targets that do not use the CodeGen
library, so we may just as well store a pointer to an
LLVMTargetMachine instead of just to a TargetMachine.

While at it, also change the constructor to take a reference instead of a
pointer as the TM must not be nullptr.

llvm-svn: 304247
2017-05-30 21:36:41 +00:00
Krzysztof Parzyszek ef58017b35 [Hexagon] Improve code generation for 32x32-bit multiplication
For multiplications of 64-bit values (giving 64-bit result), detect
cases where the arguments are sign-extended 32-bit values, on a per-
operand basis. This will allow few patterns to match a wider variety
of combinations in which extensions can occur.

llvm-svn: 304223
2017-05-30 17:47:51 +00:00
Craig Topper f6d4dc5b4a [SelectionDAG] Set ISD::FPOWI to Expand by default
Summary:
Currently FPOWI defaults to Legal and LegalizeDAG.cpp turns Legal into Expand for this opcode because Legal is a "lie".

This patch changes the default for this opcode to Expand and removes the hack from LegalizeDAG.cpp. It also removes all the code in the targets that set this opcode to Expand themselves since they can just rely on the default.

Reviewers: spatel, RKSimon, efriedma

Reviewed By: RKSimon

Subscribers: jfb, dschuff, sbc100, jgravelle-google, nemanjai, javed.absar, andrew.w.kaylor, llvm-commits

Differential Revision: https://reviews.llvm.org/D33530

llvm-svn: 304215
2017-05-30 15:27:55 +00:00
Matthias Braun ac4307c41e LivePhysRegs: Rework constructor + documentation; NFC
- Take reference instead of pointer to a TRI that cannot be nullptr.
- Improve documentation comments.

llvm-svn: 304038
2017-05-26 21:51:00 +00:00
Sumanth Gundapaneni a6cf2fd5ec [Hexagon] Cleanup of unused function isCalleeSaveReg (NFC)
llvm-svn: 304034
2017-05-26 21:09:54 +00:00
Krzysztof Parzyszek e3ec97b031 [Hexagon] Fix comment in HexagonPacketizer::runOnMachineFunction
Patch by Wei-Ren Chen.

Differential Revision: https://reviews.llvm.org/D33439

llvm-svn: 303745
2017-05-24 13:43:42 +00:00
Krzysztof Parzyszek 9a23d40ee8 [Hexagon] Fix definitions of vector predicate loads and stores
This fixes http://llvm.org/PR33048.

llvm-svn: 303572
2017-05-22 20:02:53 +00:00
Reid Kleckner 96ab8726a3 [IR] De-virtualize ~Value to save a vptr
Summary:
Implements PR889

Removing the virtual table pointer from Value saves 1% of RSS when doing
LTO of llc on Linux. The impact on time was positive, but too noisy to
conclusively say that performance improved. Here is a link to the
spreadsheet with the original data:

https://docs.google.com/spreadsheets/d/1F4FHir0qYnV0MEp2sYYp_BuvnJgWlWPhWOwZ6LbW7W4/edit?usp=sharing

This change makes it invalid to directly delete a Value, User, or
Instruction pointer. Instead, such code can be rewritten to a null check
and a call Value::deleteValue(). Value objects tend to have their
lifetimes managed through iplist, so for the most part, this isn't a big
deal.  However, there are some places where LLVM deletes values, and
those places had to be migrated to deleteValue.  I have also created
llvm::unique_value, which has a custom deleter, so it can be used in
place of std::unique_ptr<Value>.

I had to add the "DerivedUser" Deleter escape hatch for MemorySSA, which
derives from User outside of lib/IR. Code in IR cannot include MemorySSA
headers or call the MemoryAccess object destructors without introducing
a circular dependency, so we need some level of indirection.
Unfortunately, no class derived from User may have any virtual methods,
because adding a virtual method would break User::getHungOffOperands(),
which assumes that it can find the use list immediately prior to the
User object. I've added a static_assert to the appropriate OperandTraits
templates to help people avoid this trap.

Reviewers: chandlerc, mehdi_amini, pete, dberlin, george.burgess.iv

Reviewed By: chandlerc

Subscribers: krytarowski, eraman, george.burgess.iv, mzolotukhin, Prazek, nlewycky, hans, inglorion, pcc, tejohnson, dberlin, llvm-commits

Differential Revision: https://reviews.llvm.org/D31261

llvm-svn: 303362
2017-05-18 17:24:10 +00:00
Francis Visoiu Mistrih 8b61764cbb [LegacyPassManager] Remove TargetMachine constructors
This provides a new way to access the TargetMachine through
TargetPassConfig, as a dependency.

The patterns replaced here are:

* Passes handling a null TargetMachine call
  `getAnalysisIfAvailable<TargetPassConfig>`.

* Passes not handling a null TargetMachine
  `addRequired<TargetPassConfig>` and call
  `getAnalysis<TargetPassConfig>`.

* MachineFunctionPasses now use MF.getTarget().

* Remove all the TargetMachine constructors.
* Remove INITIALIZE_TM_PASS.

This fixes a crash when running `llc -start-before prologepilog`.

PEI needs StackProtector, which gets constructed without a TargetMachine
by the pass manager. The StackProtector pass doesn't handle the case
where there is no TargetMachine, so it segfaults.

Related to PR30324.

Differential Revision: https://reviews.llvm.org/D33222

llvm-svn: 303360
2017-05-18 17:21:13 +00:00
Craig Topper 8df66c602a [KnownBits] Add bit counting methods to KnownBits struct and use them where possible
This patch adds min/max population count, leading/trailing zero/one bit counting methods.

The min methods return answers based on bits that are known without considering unknown bits. The max methods give answers taking into account the largest count that unknown bits could give.

Differential Revision: https://reviews.llvm.org/D32931

llvm-svn: 302925
2017-05-12 17:20:30 +00:00
Serge Pavlov d526b13e61 Add extra operand to CALLSEQ_START to keep frame part set up previously
Using arguments with attribute inalloca creates problems for verification
of machine representation. This attribute instructs the backend that the
argument is prepared in stack prior to  CALLSEQ_START..CALLSEQ_END
sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size
stored in CALLSEQ_START in this case does not count the size of this
argument. However CALLSEQ_END still keeps total frame size, as caller can
be responsible for cleanup of entire frame. So CALLSEQ_START and
CALLSEQ_END keep different frame size and the difference is treated by
MachineVerifier as stack error. Currently there is no way to distinguish
this case from actual errors.

This patch adds additional argument to CALLSEQ_START and its
target-specific counterparts to keep size of stack that is set up prior to
the call frame sequence. This argument allows MachineVerifier to calculate
actual frame size associated with frame setup instruction and correctly
process the case of inalloca arguments.

The changes made by the patch are:
- Frame setup instructions get the second mandatory argument. It
  affects all targets that use frame pseudo instructions and touched many
  files although the changes are uniform.
- Access to frame properties are implemented using special instructions
  rather than calls getOperand(N).getImm(). For X86 and ARM such
  replacement was made previously.
- Changes that reflect appearance of additional argument of frame setup
  instruction. These involve proper instruction initialization and
  methods that access instruction arguments.
- MachineVerifier retrieves frame size using method, which reports sum of
  frame parts initialized inside frame instruction pair and outside it.

The patch implements approach proposed by Quentin Colombet in
https://bugs.llvm.org/show_bug.cgi?id=27481#c1.
It fixes 9 tests failed with machine verifier enabled and listed
in PR27481.

Differential Revision: https://reviews.llvm.org/D32394

llvm-svn: 302527
2017-05-09 13:35:13 +00:00
Krzysztof Parzyszek ee93e009c8 [Hexagon] Disable predicated calls by default
llvm-svn: 302307
2017-05-05 22:13:57 +00:00
Krzysztof Parzyszek e260332838 [Hexagon] Remove C6 and C7 as separate registers
These are M0 and M1. Removing duplicated registers reduces the number
of explicit register aliasing.

llvm-svn: 302306
2017-05-05 22:12:12 +00:00
Krzysztof Parzyszek d0c71ef8ab [RDF] Remove covered parts of reached uses for phi and use in same block
llvm-svn: 302305
2017-05-05 22:10:32 +00:00
Krzysztof Parzyszek 2af5037d34 [Hexagon] Use automatically-generated scheduling information for HVX
Patch by Jyotsna Verma.

llvm-svn: 302073
2017-05-03 20:10:36 +00:00
Krzysztof Parzyszek d10df49c90 [Hexagon] Handle S2_storerf_io in HexagonInstrInfo
llvm-svn: 302036
2017-05-03 15:36:51 +00:00
Krzysztof Parzyszek 700a5f99c7 [Hexagon] Misc fixes in HexagonInstrInfo, NFC
Formatting changes + remove unused function.

llvm-svn: 302035
2017-05-03 15:34:52 +00:00
Krzysztof Parzyszek 4763c2d999 [Hexagon] Adjust latency between allocframe and the first store on stack
Allocframe and the following stores on the stack have a latency of 2 cycles
when not in the same packet. This happens because R29 is needed early by the
store instruction. Since one of such stores can be packetized along with
allocframe and use old value of R29, we can assign it 0 cycle latency
while leaving latency of other stores to the default value of 2 cycles.

Patch by Jyotsna Verma.

llvm-svn: 302034
2017-05-03 15:33:09 +00:00
Krzysztof Parzyszek 19635bdcbb [Hexagon] Handle J2_jumptpt and J2_jumpfpt in HexagonInstrInfo
llvm-svn: 302033
2017-05-03 15:30:46 +00:00
Krzysztof Parzyszek 0a8043e1b3 [Hexagon] Implement undoing .cur instructions in packetizer
The packetizer needs to convert .cur instruction to its regular form if
the use is not in the same packet as the .cur. The code in the packetizer
handles one type of .cur, which is the vector load case. This patch
updates the packetizer so that it can undo all the .cur instructions.
In the test case, the .cur is the 128B version, but there are also the
post-increment versions.

Patch by Brendon Cahoon.

llvm-svn: 302032
2017-05-03 15:28:56 +00:00
Krzysztof Parzyszek 4be9d92b69 [Hexagon] Add memory operands to a rewritten load
llvm-svn: 302030
2017-05-03 15:26:13 +00:00
Krzysztof Parzyszek 781324fc7e [Hexagon] Reset spill alignment when variable-sized objects are present
llvm-svn: 302029
2017-05-03 15:23:53 +00:00
Krzysztof Parzyszek fca6fae463 [Hexagon] Fix uninitialized value caught with valgrind
Patch by Colin LeMahieu.

llvm-svn: 301957
2017-05-02 18:29:49 +00:00
Krzysztof Parzyszek 57a8bb4343 [Hexagon] Change iconst to emit 27bit relocation
Patch by Colin LeMahieu.

llvm-svn: 301956
2017-05-02 18:19:11 +00:00
Krzysztof Parzyszek a750383d0f [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCREL
Patch by Sid Manning.

llvm-svn: 301955
2017-05-02 18:15:33 +00:00
Krzysztof Parzyszek 9aaf923376 [Hexagon] Don't ignore mult-cycle latency information
The compiler was generating code that ends up ignoring a multiple
latency dependence between two instructions by scheduling the
intructions in back-to-back packets. 

The packetizer needs to end a packet if the latency of the current
current insruction and the source in the previous packet is
greater than 1 cycle. This case occurs when there is still room in
the current packet, but scheduling the instruction causes a stall.
Instead, the packetizer should start a new packet. Also, if the
current packet already contains a stall, then it is okay to add
another instruction to the packet that also causes a stall. This
occurs when there are no instructions that can be scheduled in
between the producer and consumer instructions.

This patch changes the latency for loads to 2 cycles from 3 cycles.
This change refects that a load only needs to be separated by
one extra packet to eliminate the stall.

Patch by Ikhlas Ajbar.

llvm-svn: 301954
2017-05-02 18:12:19 +00:00
Krzysztof Parzyszek 32e20b80c6 [Hexagon] Formatting changes, NFC
llvm-svn: 301953
2017-05-02 18:09:07 +00:00
Krzysztof Parzyszek 188ab98f67 [Hexagon] Remove unused validSubtarget TSFlags
Patch by Colin LeMahieu.

llvm-svn: 301952
2017-05-02 18:05:36 +00:00
Krzysztof Parzyszek b0af1ef741 [Hexagon] Make sure duplexed dealloc_returns are checked for double jumps
Patch by Colin LeMahieu.

llvm-svn: 301951
2017-05-02 18:03:08 +00:00
Krzysztof Parzyszek 49f7e0a98b [Hexagon] Move checking AXOK to checker
Patch by Colin LeMahieu.

llvm-svn: 301949
2017-05-02 18:00:37 +00:00
Krzysztof Parzyszek 57f5046b4a [Hexagon] Remove unneeded code from HexagonShuffler
Patch by Colin LeMahieu.

llvm-svn: 301947
2017-05-02 17:58:52 +00:00
Krzysztof Parzyszek c15f8d2a08 [Hexagon] Extract function that checks endloops with other branches
Change location number to point to conflicting branch instruction.

Patch by Colin LeMahieu.

llvm-svn: 301946
2017-05-02 17:56:11 +00:00
Krzysztof Parzyszek 1cc6bfbc83 [Hexagon] Add new packet iterator which will iterate through duplexes
Patch by Colin LeMahieu.

llvm-svn: 301945
2017-05-02 17:53:51 +00:00
Krzysztof Parzyszek 107f82d128 [Hexagon] Check for .cur def without use without using a map data structure
Patch by Colin LeMahieu.

llvm-svn: 301943
2017-05-02 17:51:14 +00:00
Krzysztof Parzyszek 4a1c3f0aaa [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LD
A .cur instruction can be identified by checking isCVINew() && mayLoad().

Patch by Colin LeMahieu.

llvm-svn: 301829
2017-05-01 20:16:35 +00:00
Krzysztof Parzyszek 55db483a46 [Hexagon] Improving error reporting for writing to read only registers
Patch by Colin LeMahieu.

llvm-svn: 301828
2017-05-01 20:10:41 +00:00
Krzysztof Parzyszek e96d27a997 [Hexagon] Give better error messages for solo instruction errors
Patch by Colin LeMahieu.

llvm-svn: 301827
2017-05-01 20:06:01 +00:00