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19 Commits

Author SHA1 Message Date
Andrew Kaylor a2b9111ef7 Add optimization bisect opt-in calls for ARM passes 
Differential Revision: http://reviews.llvm.org/D19449

llvm-svn: 267480
 2016-04-25 22:01:04 +00:00
Benjamin Kramer 799003bf8c Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 
llvm-svn: 232998
 2015-03-23 19:32:43 +00:00
Eric Christopher 63b44882ef Cleanup and remove a chunk of getARMSubtarget calls in the 
ARM TargetMachine pass pipeline construction by pushing them down
into the appropriate pass.

llvm-svn: 231323
 2015-03-05 00:23:40 +00:00
Eric Christopher 4c67d5a1e3 Include map into the A15SDOptimizer rather than pick it up 
transitively from the DFAPacketizer via TargetInstrInfo.h.

llvm-svn: 219652
 2014-10-14 01:13:51 +00:00
Eric Christopher fc6de428c8 Have MachineFunction cache a pointer to the subtarget to make lookups 
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

llvm-svn: 214838
 2014-08-05 02:39:49 +00:00
Eric Christopher d913448b38 Remove the TargetMachine forwards for TargetSubtargetInfo based 
information and update all callers. No functional change.

llvm-svn: 214781
 2014-08-04 21:25:23 +00:00
Craig Topper 35b2f75733 Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert. 
llvm-svn: 211254
 2014-06-19 06:10:58 +00:00
Craig Topper 062a2baef0 [C++] Use 'nullptr'. Target edition. 
llvm-svn: 207197
 2014-04-25 05:30:21 +00:00
Chandler Carruth 84e68b2994 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE 
definition below all of the header #include lines, lib/Target/...
edition.

llvm-svn: 206842
 2014-04-22 02:41:26 +00:00
Jim Grosbach 1a59711505 Tidy up. Trailing whitespace. 
llvm-svn: 205583
 2014-04-03 23:43:18 +00:00
Craig Topper a9253267a9 Prune includes in ARM target. 
llvm-svn: 204548
 2014-03-22 23:51:00 +00:00
Hao Liu 40b5ab8e5b [ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR. 
llvm-svn: 204304
 2014-03-20 05:36:59 +00:00
Owen Anderson 16c6bf49b7 Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing 
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&.  At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.

llvm-svn: 203865
 2014-03-13 23:12:04 +00:00
Craig Topper 6bc27bf359 [C++11] Add 'override' keyword to virtual methods that override their base class. 
llvm-svn: 203433
 2014-03-10 02:09:33 +00:00
Chandler Carruth 8a8cd2bab9 Re-sort all of the includes with ./utils/sort_includes.py so that 
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

llvm-svn: 198685
 2014-01-07 11:48:04 +00:00
Alp Toker f907b891da Correct word hyphenations 
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.

llvm-svn: 196471
 2013-12-05 05:44:44 +00:00
Jim Grosbach 13654dd303 ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane. 
These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.

I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).

PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093
llvm-svn: 189972
 2013-09-04 19:08:44 +00:00
Craig Topper 31ee5866de Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. 
llvm-svn: 185540
 2013-07-03 15:07:05 +00:00
Silviu Baranga 82dd6ac3bc Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc. 
llvm-svn: 177169
 2013-03-15 18:28:25 +00:00