llvm-project

Commit Graph

Author	SHA1	Message	Date
Stanislav Mekhanoshin	3bffb1cd0e	[AMDGPU] Use single cache policy operand Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469	2021-03-15 13:00:59 -07:00
Stanislav Mekhanoshin	a8d9d50762	[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906	2021-02-17 16:01:32 -08:00
Jay Foad	47788b97a9	SILoadStoreOptimizer: add support for GFX10 image instructions GFX10 image instructions use one or more address operands starting at vaddr0, instead of a single vaddr operand, to allow for NSA forms. Differential Revision: https://reviews.llvm.org/D81675	2020-07-08 19:15:46 +01:00

Author

SHA1

Message

Date

Stanislav Mekhanoshin

3bffb1cd0e

[AMDGPU] Use single cache policy operand

Replace individual operands GLC, SLC, and DLC with a single cache_policy
bitmask operand. This will reduce the number of operands in MIR and I hope
the amount of code. These operands are mostly 0 anyway.

Additional advantage that parser will accept these flags in any order unlike
now.

Differential Revision: https://reviews.llvm.org/D96469

2021-03-15 13:00:59 -07:00

Stanislav Mekhanoshin

a8d9d50762

[AMDGPU] gfx90a support

Differential Revision: https://reviews.llvm.org/D96906

2021-02-17 16:01:32 -08:00

Jay Foad

47788b97a9

SILoadStoreOptimizer: add support for GFX10 image instructions

GFX10 image instructions use one or more address operands starting at
vaddr0, instead of a single vaddr operand, to allow for NSA forms.

Differential Revision: https://reviews.llvm.org/D81675

2020-07-08 19:15:46 +01:00

3 Commits