b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
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that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
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zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
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for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
557c8e3443
Add patterns for unaligned load and store instructions and enable the
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instruction selector to generate them.
llvm-svn: 141471
2011-10-08 02:24:10 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
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llvm-svn: 141024
2011-10-03 21:06:13 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
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registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
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llvm-svn: 140443
2011-09-24 01:34:44 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
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complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
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llvm-svn: 140214
2011-09-20 23:53:09 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
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tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
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llvm-svn: 139405
2011-09-09 20:45:50 +00:00
2b8078a2cd
Clenup and fix encoding for Mips ins and ext instruction
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llvm-svn: 137943
2011-08-18 16:30:49 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
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llvm-svn: 137892
2011-08-17 22:59:46 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
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llvm-svn: 137848
2011-08-17 18:49:18 +00:00
5360f88355
Add support for ext and ins.
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llvm-svn: 137804
2011-08-17 02:05:42 +00:00
2fcc1cfdce
Define unaligned load and store.
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llvm-svn: 137515
2011-08-12 21:30:06 +00:00
6d8c039ab1
Add isIndirectBranch flag.
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llvm-svn: 137351
2011-08-11 21:05:37 +00:00
170581488f
Change name of class.
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llvm-svn: 135550
2011-07-20 00:53:09 +00:00
969edcdf74
Define classes for definitions of atomic instructions.
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llvm-svn: 135546
2011-07-20 00:23:01 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
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llvm-svn: 135537
2011-07-19 23:30:50 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
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moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
28d6677a53
Remove unnecessary newline.
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llvm-svn: 134645
2011-07-07 22:06:18 +00:00
9f6f6f6ecc
Rather than having printMemOperand change the way memory operands are printed
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based on a modifier, split it into two functions.
llvm-svn: 134637
2011-07-07 20:54:20 +00:00
2e766ed2f8
Reverse order of operands of address operand mem so that the base operand comes
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before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134625
2011-07-07 18:57:00 +00:00
4c406e7457
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
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llvm-svn: 133494
2011-06-21 00:40:49 +00:00
f15601f19a
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
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llvm-svn: 132777
2011-06-09 16:03:19 +00:00
4e9af454f7
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
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dynamically allocated stack area was not set.
llvm-svn: 132758
2011-06-08 21:28:09 +00:00
d8373a4680
Add comments for wrapper node patterns in MipsInstrInfo.td.
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llvm-svn: 132717
2011-06-07 18:00:14 +00:00
98fc4c8bbc
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
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nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
llvm-svn: 132323
2011-05-31 02:54:07 +00:00
bf3c1251e0
This patch implements the thread local storage. Implemented are General
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Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
llvm-svn: 132322
2011-05-31 02:53:58 +00:00
b406843fe5
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
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Need this to prevent emitting illegal conditional move instructions.
llvm-svn: 132240
2011-05-28 01:07:07 +00:00
46662e0f91
Coding style fixes. Added comments.
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llvm-svn: 132063
2011-05-25 17:32:06 +00:00
2db176c4c1
Enable printing of immediates that do not fit in 16-bit. .cprestore can have
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offsets that are larger than 0x10000.
llvm-svn: 132003
2011-05-24 21:22:21 +00:00
e50a3d16e9
Fix setting of isCommutable flag.
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llvm-svn: 131233
2011-05-12 17:42:08 +00:00
5dc19f916c
Fix td file comments for Mips.
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Patch by Liu <proljc@gmail.com>!
llvm-svn: 131086
2011-05-09 18:16:46 +00:00
0e7ee666b7
Lower BlockAddress node when relocation-model is static.
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llvm-svn: 130131
2011-04-25 17:10:45 +00:00
e24891251c
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
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llvm-svn: 129612
2011-04-15 21:51:11 +00:00
aef55c8801
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
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llvm-svn: 129606
2011-04-15 21:00:26 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
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llvm-svn: 128650
2011-03-31 18:26:17 +00:00
434248a62c
Improve div/rem node handling on mips. Patch by Akira Hatanaka
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llvm-svn: 127034
2011-03-04 21:03:24 +00:00
a744ef3f90
Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka
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llvm-svn: 127032
2011-03-04 20:48:08 +00:00
f8198e4311
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
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llvm-svn: 127027
2011-03-04 20:01:52 +00:00
db93ddb41b
Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka
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llvm-svn: 127005
2011-03-04 17:59:18 +00:00
ed874eff93
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
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llvm-svn: 127003
2011-03-04 17:51:39 +00:00
4dc73fa075
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka
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llvm-svn: 123760
2011-01-18 19:29:17 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
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llvm-svn: 122513
2010-12-23 18:28:41 +00:00
d47180e45e
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
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llvm-svn: 121377
2010-12-09 17:32:30 +00:00
b9bfd0945a
Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again
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llvm-svn: 121164
2010-12-07 19:04:14 +00:00
f0c6e3780d
Match a pattern generated by a dag combiner opt where:
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(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))
Thanks to Akira for pointing that.
llvm-svn: 121163
2010-12-07 19:00:20 +00:00
03c0330176
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
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llvm-svn: 118864
2010-11-12 00:38:32 +00:00
Akira Hatanaka