Commit Graph

5207 Commits

Author SHA1 Message Date
Jim Grosbach 45e50d8a0b ARM .align NOP padding uses different encoding pre-ARMv6.
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
2011-08-16 17:06:20 +00:00
Owen Anderson a6201f0a72 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
llvm-svn: 137686
2011-08-15 23:38:54 +00:00
Jim Grosbach 120a96a721 MCTargetAsmParser target match predicate support.
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675
2011-08-15 23:03:29 +00:00
Owen Anderson 1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.

llvm-svn: 137647
2011-08-15 20:51:32 +00:00
Owen Anderson de25f9aa8f Remove dead classes.
llvm-svn: 137643
2011-08-15 20:11:11 +00:00
Owen Anderson 61a3ece665 Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
Owen Anderson 3157f2eebe Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
Owen Anderson b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
Jim Grosbach 30694dcdeb Update comment to reflect MC target machine refactor.
llvm-svn: 137615
2011-08-15 16:52:24 +00:00
Bob Wilson d1de7764be Expand VMOVQQQQ pseudo instructions.
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551
2011-08-13 05:14:55 +00:00
Jim Grosbach 2325474368 ARM STR_POST_IMM offset encoding fix in load/store optimizer.
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.

rdar://9945172

llvm-svn: 137525
2011-08-12 22:20:41 +00:00
Jim Grosbach f402f694e2 ARM expansion of pre-indexed store pseudos should maintain memoperands.
Partial fix for rdar://9945172.

llvm-svn: 137513
2011-08-12 21:02:34 +00:00
Owen Anderson 2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
Owen Anderson 60138eaf93 Fix decoding of ARM-mode STRH.
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
Owen Anderson 1043e173bc Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
llvm-svn: 137494
2011-08-12 19:41:29 +00:00
Owen Anderson 3987a61c16 Fix decoding of pre-indexed stores.
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
Owen Anderson c5798a3a59 Separate decoding for STREXD and LDREXD to make each work better.
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
Duncan Sands a41634e307 Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.

llvm-svn: 137460
2011-08-12 14:54:45 +00:00
Jim Grosbach 8cffa28af8 ARM vector compare to zero instruction assembly parsing support.
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
Jim Grosbach 37f7e6b2f4 Remove no-longer-true comments. These are for the assembler, also.
llvm-svn: 137375
2011-08-11 22:30:30 +00:00
Jim Grosbach e25942154c ARM STRT assembly parsing and encoding.
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Owen Anderson eca346ee1a Make the USAT16 operand decoder auto-generate-able.
llvm-svn: 137371
2011-08-11 22:10:11 +00:00
Owen Anderson ff0b442330 Add another accidentally omitted predicate operand.
llvm-svn: 137370
2011-08-11 22:08:38 +00:00
Owen Anderson 2f7aa73312 Add missing predicate operand on SMLA and friends.
llvm-svn: 137368
2011-08-11 22:05:38 +00:00
Jim Grosbach a2b8b60646 ARM load shifted register pre-index fix shift value asm parser encoding.
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
Owen Anderson 12d13efa21 Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
llvm-svn: 137364
2011-08-11 21:52:38 +00:00
Owen Anderson f05e744857 Making SEL decodings auto-generate-able.
llvm-svn: 137363
2011-08-11 21:50:56 +00:00
Jim Grosbach 88981ff168 Tidy up comment.
llvm-svn: 137359
2011-08-11 21:41:59 +00:00
Owen Anderson b685c9f011 Fix decoding support for STREXD and LDREXD.
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding.
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
Owen Anderson 3a850f28d0 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
Jim Grosbach 2ea19d1438 Tidy up. Remove unused template parameter.
llvm-svn: 137345
2011-08-11 20:41:13 +00:00
Owen Anderson 887c0b1358 Improve operand validation for Thumb2 addressing modes.
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding.
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
Owen Anderson 6066340301 Continue to tighten decoding by performing more operand validation.
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach 1b0f79573e Tidy up.
llvm-svn: 137339
2011-08-11 20:13:35 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding.
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding.
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Owen Anderson 3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Owen Anderson ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy.
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Jim Grosbach d5d6359785 ARM LDRT assembly parsing and encoding.
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Jim Grosbach d3f7bcd43c Tidy up. 80 columns.
llvm-svn: 137277
2011-08-10 23:23:47 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support.
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Jim Grosbach f7164b2cfd Fix typo. Not quite sure how that slipped in there.
llvm-svn: 137245
2011-08-10 20:49:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support.
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Owen Anderson c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode.
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson 1531e5cd2b Tabs --> spaces.
llvm-svn: 137225
2011-08-10 17:38:05 +00:00
Owen Anderson 5d69f63bbb Cleanups based on Nick Lewycky's feedback.
llvm-svn: 137224
2011-08-10 17:36:48 +00:00
Owen Anderson 732f82c463 Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
llvm-svn: 137223
2011-08-10 17:21:20 +00:00
Rafael Espindola 36a3abc671 Add support for the R and Q constraints.
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
Owen Anderson 8059f0cf8d Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Jakob Stoklund Olesen 6a14dc01ff Promote VMOVS to VMOVD when possible.
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.

This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline.  Example:

        vldr.32 s0, LCPI0_0
    loop:
        vorr    d1, d0, d0
    loop2:
        ...
        vadd.f32        d1, d1, d16

The vorr instruction looked like this after regalloc:

    %S2<def> = COPY %S0, %D1<imp-def>

Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.

llvm-svn: 137182
2011-08-09 23:41:44 +00:00
Owen Anderson 92b942b1b5 Tighten operand checking of register-shifted-register operands.
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson e008931bf6 Tighten operand checking on memory barrier instructions.
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson 3d2e0e9db6 Tighten operand checking on CPS instructions.
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson 042619f97d Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Benjamin Kramer 406dc1755f ARM Disassembler: sign extend branch immediates.
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
2011-08-09 22:02:50 +00:00
Owen Anderson d151b09921 Silence an false-positive warning.
llvm-svn: 137154
2011-08-09 21:38:14 +00:00
Owen Anderson d770f6c110 Don't generate the old-style disassembler in CMake builds either.
llvm-svn: 137153
2011-08-09 21:36:11 +00:00
Benjamin Kramer de2c381331 The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
llvm-svn: 137151
2011-08-09 21:34:19 +00:00
Owen Anderson 982aa05017 Don't continue generating the old-style decoder file.
llvm-svn: 137150
2011-08-09 21:30:29 +00:00
Jim Grosbach 5e80abbb5d ARM fix typo in pre-indexed store lowering.
rdar://9915869

llvm-svn: 137148
2011-08-09 21:22:41 +00:00
Owen Anderson c7afd84322 Attempt to fix CMake build.
llvm-svn: 137147
2011-08-09 21:09:59 +00:00
Owen Anderson 7a2401dbf0 Tighten Thumb1 branch predicate decoding.
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
Owen Anderson e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Renato Golin faff512536 Emitting ARM build attributes and values as ULEB, rather than char.
llvm-svn: 137115
2011-08-09 09:50:10 +00:00
Jim Grosbach cab35c0836 ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
2011-08-08 23:28:47 +00:00
Owen Anderson 03ac20fc66 Thumb1 BL instructions encoding 22 bits of displacement, not 21.
llvm-svn: 137073
2011-08-08 23:25:22 +00:00
Jakob Stoklund Olesen c04a66b48e Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
They improve the verbose assembly.

llvm-svn: 137069
2011-08-08 21:45:32 +00:00
Jim Grosbach 95466ce63b ARM load/store label parsing.
Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.

llvm-svn: 137064
2011-08-08 20:59:31 +00:00
Owen Anderson c40303885b Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
llvm-svn: 137062
2011-08-08 20:42:17 +00:00
Eli Friedman a27da98921 Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
llvm-svn: 137061
2011-08-08 19:49:37 +00:00
Benjamin Kramer c22d50e5c3 Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

llvm-svn: 137059
2011-08-08 18:56:44 +00:00
Jim Grosbach 3d0b3a3a50 ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
2011-08-05 22:03:36 +00:00
Jim Grosbach c320c85261 ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
2011-08-05 21:28:30 +00:00
Jim Grosbach f0c95cadc7 ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.

llvm-svn: 136978
2011-08-05 20:35:44 +00:00
Jim Grosbach a70fbfd577 ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969
2011-08-05 16:11:38 +00:00
Jim Grosbach bafce840ff ARM use a dedicated printer for postidx_reg operands.
llvm-svn: 136968
2011-08-05 15:48:21 +00:00
Bob Wilson 8de11bab76 Add missing register constraint for some VLD3/VLD4 pseudo instructions.
<rdar://problem/9878189>

llvm-svn: 136962
2011-08-05 07:24:09 +00:00
Owen Anderson 08d4bb0f12 Fix broken encodings for the Thumb2 LDRD/STRD instructions.
llvm-svn: 136942
2011-08-04 23:18:05 +00:00
Jim Grosbach cd17c12078 ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.

llvm-svn: 136940
2011-08-04 23:01:30 +00:00
Owen Anderson ce5190321e LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
llvm-svn: 136896
2011-08-04 18:24:14 +00:00
Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Owen Anderson 7bc3b11a56 Fix broken encoding of tCBNZ.
llvm-svn: 136837
2011-08-03 23:21:48 +00:00
Eli Friedman 30a49e93e3 New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
2011-08-03 21:06:02 +00:00
Eli Friedman 5c863aeefd ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.
llvm-svn: 136737
2011-08-02 22:44:16 +00:00
Owen Anderson 713406f88d Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
llvm-svn: 136707
2011-08-02 18:30:00 +00:00
Jim Grosbach c8c63914c5 Tidy up. 80 columns.
llvm-svn: 136705
2011-08-02 18:16:36 +00:00
Jim Grosbach 9ec152b6bf ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704
2011-08-02 18:07:32 +00:00
Jim Grosbach 9f620a6883 Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
llvm-svn: 136656
2011-08-01 22:02:20 +00:00
Jim Grosbach 0f731b3232 Fix comments.
llvm-svn: 136655
2011-08-01 21:55:12 +00:00
Douglas Gregor d41f3a161f Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC.
llvm-svn: 136621
2011-08-01 16:29:27 +00:00
Eric Christopher aa5030066f Add support for the 'Q' constraint.
Fixes rdar://9866494

llvm-svn: 136523
2011-07-29 21:18:58 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach e537438ca5 ARM CPS mode immediate is 5 bits, not 4.
llvm-svn: 136505
2011-07-29 20:02:39 +00:00
Jim Grosbach c4dc52cd52 ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Jim Grosbach 20d38124a2 ARM SRS and RFE instructions are not code-gen only.
llvm-svn: 136475
2011-07-29 17:51:39 +00:00
Jim Grosbach 3b764cfd48 ARM range checking for mode on CPS instruction.
llvm-svn: 136473
2011-07-29 17:42:17 +00:00
Jim Grosbach e658f4faeb Update FIXME.
llvm-svn: 136470
2011-07-29 17:36:04 +00:00
Jim Grosbach 47859c8ab0 Tweak comment.
llvm-svn: 136468
2011-07-29 17:33:29 +00:00
Jakob Stoklund Olesen b28ee4115d Transfer implicit operands in NEONMoveFixPass.
Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

llvm-svn: 136440
2011-07-29 00:27:35 +00:00
Jakob Stoklund Olesen 9c3badceba Add -verify-arm-pseudo-expand.
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

llvm-svn: 136439
2011-07-29 00:27:32 +00:00
Chandler Carruth 9d7feab3e0 Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

llvm-svn: 136433
2011-07-29 00:14:25 +00:00
Jim Grosbach dd475c39d7 PLD and PLI are not predicable in ARM mode.
llvm-svn: 136427
2011-07-28 23:22:41 +00:00
Jim Grosbach a03ab0e3dc ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406
2011-07-28 21:57:55 +00:00
Jim Grosbach 864b609491 ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399
2011-07-28 21:34:26 +00:00
Jim Grosbach bfb439b140 Add fixme.
llvm-svn: 136375
2011-07-28 19:46:12 +00:00
Owen Anderson 7c965e7520 Update comments.
llvm-svn: 136367
2011-07-28 17:56:55 +00:00
Owen Anderson 301f793ed5 Fill in some encoding information for STRD instructions.
llvm-svn: 136366
2011-07-28 17:53:25 +00:00
Owen Anderson b0e6899398 Revert r136295. It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now.
llvm-svn: 136362
2011-07-28 17:18:57 +00:00
Jim Grosbach 8b3184e540 ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.

llvm-svn: 136360
2011-07-28 16:33:54 +00:00
Oscar Fuentes a8666a3cdb Explicitly declare a library dependency of LLVM*Desc to
LLVM*AsmPrinter.

GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:

../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'

llvm-svn: 136328
2011-07-28 02:33:52 +00:00
Owen Anderson b81af2abe0 Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.
llvm-svn: 136295
2011-07-27 23:36:57 +00:00
Evan Cheng eda1d4f3ba Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Jim Grosbach 57e2d3cb84 ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285
2011-07-27 22:34:17 +00:00
Eli Friedman 26a484852e Code generation for 'fence' instruction.
llvm-svn: 136283
2011-07-27 22:21:52 +00:00
Jim Grosbach 39b062bfaa ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277
2011-07-27 22:01:42 +00:00
Jim Grosbach 0c398b9c7e ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274
2011-07-27 21:58:11 +00:00
Jim Grosbach 03f56d9de6 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Owen Anderson fa9e6d43a0 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
llvm-svn: 136255
2011-07-27 20:29:48 +00:00
Jim Grosbach 833b9d3353 ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252
2011-07-27 20:15:40 +00:00
Jim Grosbach 66ee037863 ARM assembly parsing aliases for extend instructions w/o rotate.
llvm-svn: 136229
2011-07-27 18:19:32 +00:00
Jim Grosbach 38b5503d21 ARM cleanup of remaining extend instructions.
Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.

llvm-svn: 136226
2011-07-27 17:48:13 +00:00
Jim Grosbach 8b31ef50c0 ARM extend instructions simplification.
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.

llvm-svn: 136225
2011-07-27 16:47:19 +00:00
Evan Cheng 481ebb0133 Support .code32 and .code64 in X86 assembler.
llvm-svn: 136197
2011-07-27 00:38:12 +00:00
Jim Grosbach a5f7a8cfde ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.

llvm-svn: 136154
2011-07-26 21:44:37 +00:00
Jim Grosbach d2659138da ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152
2011-07-26 21:28:43 +00:00
Owen Anderson 2aedba6c5e Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
llvm-svn: 136141
2011-07-26 20:54:26 +00:00
Jim Grosbach 0d6022da6b Fix over-zealous rename from r136095.
llvm-svn: 136132
2011-07-26 20:41:24 +00:00
Jim Grosbach edaa35ae6f ARM diagnostics for ldrexd/stredx out of order paired register operands.
llvm-svn: 136110
2011-07-26 18:25:39 +00:00
Jim Grosbach cb31193670 ARM fix for LDREX source register encoding.
rdar://9842203

llvm-svn: 136102
2011-07-26 17:44:46 +00:00
Jim Grosbach 15e8d74231 ARM assembly parsing and encoding for SWP[B] instructions.
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
Jim Grosbach dbc1c5479e ARM SWP instructions store, too, not just load.
llvm-svn: 136096
2011-07-26 17:11:05 +00:00
Jim Grosbach eab1c0d09c Clean up the ARM asm parser a bit.
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.

llvm-svn: 136095
2011-07-26 17:10:22 +00:00
Jim Grosbach ddeda0fad3 ARM fix asm parsing range check for [0,31] immediates.
llvm-svn: 136091
2011-07-26 16:44:05 +00:00
Jim Grosbach f16378479b ARM parsing and encoding for SVC instruction.
llvm-svn: 136090
2011-07-26 16:24:27 +00:00
Evan Cheng 3a79225b4c Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
llvm-svn: 136031
2011-07-26 00:42:34 +00:00
Evan Cheng 1142444565 Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
llvm-svn: 136027
2011-07-26 00:24:13 +00:00
Chandler Carruth 97c069c1d2 Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

llvm-svn: 136023
2011-07-26 00:09:08 +00:00
Evan Cheng 5928e69d20 Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
llvm-svn: 136010
2011-07-25 23:24:55 +00:00
Jim Grosbach 475c6dbef6 ARM assembly parsing and encoding for SSAT16 instruction.
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
Jim Grosbach 3a9cbeed73 ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.

llvm-svn: 135990
2011-07-25 22:20:28 +00:00
Evan Cheng 9eec764c15 Fix more MC layering violations.
llvm-svn: 135979
2011-07-25 21:32:49 +00:00
Evan Cheng 61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration.
llvm-svn: 135974
2011-07-25 21:20:24 +00:00
Jim Grosbach 3ddf6aa503 Simply ARM so_reg MIOperandInfo definitions.
The shift immediate encoding, printing, etc. is handled directly by the
enclosing operand definition, so it should be a vanilla immediate, not a
nested complex operand (shift_imm).

llvm-svn: 135968
2011-07-25 21:04:58 +00:00
Evan Cheng f60768a14e Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore.
llvm-svn: 135963
2011-07-25 20:53:02 +00:00
Jim Grosbach ac798e1533 ARM asm operand renaming. Make things a bit more explicit.
llvm-svn: 135959
2011-07-25 20:49:51 +00:00
Jim Grosbach eeaab22166 More simple cleanup of ARM asm operand definitions.
llvm-svn: 135958
2011-07-25 20:38:18 +00:00
Evan Cheng f5bf19530b Code clean up.
llvm-svn: 135954
2011-07-25 20:18:48 +00:00
Jim Grosbach 2d6ef44d39 Make assembly parser method names more consistent.
llvm-svn: 135950
2011-07-25 20:14:50 +00:00
Jim Grosbach 46d575acc6 Tidy up formatting.
Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.

llvm-svn: 135946
2011-07-25 20:06:30 +00:00
Jim Grosbach 5ed9fe8037 Tidy up a bit.
llvm-svn: 135945
2011-07-25 20:00:32 +00:00
NAKAMURA Takumi 287bc6bdf6 ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.
llvm-svn: 135837
2011-07-23 01:16:22 +00:00
Evan Cheng f2596bc62a Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
llvm-svn: 135833
2011-07-23 00:45:41 +00:00
Evan Cheng ad5f485957 Sink ARM mc routines into MCTargetDesc.
llvm-svn: 135825
2011-07-23 00:00:19 +00:00
Jim Grosbach 801e0a3fde ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.

llvm-svn: 135823
2011-07-22 23:16:18 +00:00
Jim Grosbach e7e1e163db ARM assembly parsing and encoding updates.
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.

llvm-svn: 135817
2011-07-22 22:06:05 +00:00
Evan Cheng 8c886a40d2 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.

llvm-svn: 135812
2011-07-22 21:58:54 +00:00
Jim Grosbach 8dfcc0bb92 ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
2011-07-22 20:18:21 +00:00
Jim Grosbach d7c8c35301 ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.

llvm-svn: 135796
2011-07-22 20:11:20 +00:00
Owen Anderson 3fa7ca84d9 Fix test failures caused by my so_reg refactoring.
llvm-svn: 135785
2011-07-22 18:30:30 +00:00
Jim Grosbach d1f8bde10f ARM assembly parsing and encoding for SMC instruction.
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
Jim Grosbach bc9d841878 Clean up a few more comments.
These instruction definitions are for the assembler, too, not just the
disassembler.

llvm-svn: 135781
2011-07-22 18:06:01 +00:00
Jim Grosbach 163eb27c1a Tidy up.
llvm-svn: 135779
2011-07-22 18:04:10 +00:00
Jim Grosbach 39f9388a9d Thumb assembly support for SETEND instruction.
llvm-svn: 135778
2011-07-22 17:52:23 +00:00
Jim Grosbach 9afae0d01b Tidy up.
llvm-svn: 135777
2011-07-22 17:46:13 +00:00
Jim Grosbach 0a547701a4 ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.

llvm-svn: 135776
2011-07-22 17:44:50 +00:00
Jim Grosbach 41d084f807 Tidy up.
llvm-svn: 135771
2011-07-22 16:59:04 +00:00
Owen Anderson 0491270f99 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
Jim Grosbach 72e7c4f9ac ARM Asm parser range checking for [0,31] immediates.
llvm-svn: 135719
2011-07-21 23:26:25 +00:00
Jim Grosbach 2a0320c877 ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
2011-07-21 22:56:30 +00:00
Jim Grosbach 17806e6636 ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
2011-07-21 22:37:43 +00:00
Jim Grosbach 4aaae18d73 Tidy up.
llvm-svn: 135706
2011-07-21 21:26:05 +00:00
Jim Grosbach 0a8d89242f ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.

llvm-svn: 135702
2011-07-21 19:57:11 +00:00
Owen Anderson b595ed0085 Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
llvm-svn: 135693
2011-07-21 18:54:16 +00:00
Jim Grosbach 27c1e2560c ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
llvm-svn: 135682
2011-07-21 17:23:04 +00:00
Jay Foad ed8db7d9df Convert ConstantExpr::getGetElementPtr and
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.

llvm-svn: 135673
2011-07-21 14:31:17 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
Jim Grosbach a288b1c10a ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.

llvm-svn: 135626
2011-07-20 21:40:26 +00:00
Jim Grosbach 94df3be987 Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.

llvm-svn: 135617
2011-07-20 20:49:03 +00:00
Jim Grosbach a98f80095b ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.

llvm-svn: 135616
2011-07-20 20:32:09 +00:00
Jim Grosbach 8d11490771 ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596
2011-07-20 18:20:31 +00:00
Evan Cheng efd9b4240f - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
2011-07-20 07:51:56 +00:00
Evan Cheng 76792992d6 Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569
2011-07-20 05:58:47 +00:00
Jim Grosbach d25c2cdad7 Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
2011-07-19 22:45:10 +00:00
Jim Grosbach 97094d8f06 ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
2011-07-19 21:59:29 +00:00
Owen Anderson c78e03c39a Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
llvm-svn: 135524
2011-07-19 21:06:00 +00:00
Jim Grosbach 7d1e5f11ea ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521
2011-07-19 20:35:35 +00:00
Jim Grosbach 5cc3b4cd9a ARM assembly parsing for MOV (register).
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513
2011-07-19 20:10:31 +00:00
Jim Grosbach 81ebc733b4 Tidy up.
llvm-svn: 135507
2011-07-19 19:47:11 +00:00
Jim Grosbach 22ac078657 Tighten conditional for 'mov' cc_out.
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.

llvm-svn: 135506
2011-07-19 19:45:44 +00:00
Jim Grosbach 7c09e3c3f3 ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
2011-07-19 19:13:28 +00:00
Jim Grosbach b475205afd Remove unused code.
cc_out and pred operands are added during parsing via custom C++ now.

llvm-svn: 135497
2011-07-19 18:32:48 +00:00
Jim Grosbach 9720dcf70b ARM range checking for so_imm operands in assembly parsing.
llvm-svn: 135489
2011-07-19 16:50:30 +00:00
Evan Cheng 2129f59637 Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468
2011-07-19 06:37:02 +00:00
Owen Anderson 83c6c4f30e Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
llvm-svn: 135442
2011-07-18 23:25:34 +00:00
Evan Cheng 67c033e6b8 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).

llvm-svn: 135438
2011-07-18 22:29:13 +00:00
Owen Anderson eab4625763 Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause decoding conflicts in the new-style disassembler.
llvm-svn: 135434
2011-07-18 22:14:02 +00:00
Evan Cheng d60fa58ba1 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424
2011-07-18 20:57:22 +00:00
Owen Anderson 64d53620aa Re-apply r135319 with a fix for the constant island pass.
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414
2011-07-18 18:50:52 +00:00
Frits van Bommel 717d7edd3e Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.

llvm-svn: 135390
2011-07-18 12:00:32 +00:00
Chris Lattner 229907cd11 land David Blaikie's patch to de-constify Type, with a few tweaks.
llvm-svn: 135375
2011-07-18 04:54:35 +00:00
Owen Anderson 2ebff84b90 Revert r135319 in an attempt to get to unbreak testers.
llvm-svn: 135343
2011-07-16 09:17:43 +00:00
Owen Anderson d57a049e5c Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
llvm-svn: 135319
2011-07-15 22:49:31 +00:00
Owen Anderson 454e1c7abb Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
Owen Anderson 9cf6f8a9b8 Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly.
llvm-svn: 135283
2011-07-15 17:48:05 +00:00
NAKAMURA Takumi cb1a888fde Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

llvm-svn: 135269
2011-07-15 12:50:21 +00:00
Evan Cheng a83b37a9db Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
solution but it is a small step towards removing the horror that is
TargetAsmInfo.

llvm-svn: 135237
2011-07-15 02:09:41 +00:00
Chandler Carruth 9a0001aedb Major update to CMake build to reflect changes in r135219 in the
backend. Moved some MCAsmInfo files down into the MCTargetDesc
sublibraries, removed some (i suspect long) dead files from other parts
of the CMake build, etc. Also copied the include directory hack from the
Makefile.

Finally, updated the lib deps. I spot checked this, and think its
correct, but review appreciated there.

llvm-svn: 135234
2011-07-15 00:40:52 +00:00
Evan Cheng 1705ab00ab Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
llvm-svn: 135219
2011-07-14 23:50:31 +00:00
Jim Grosbach 03a8a16f32 ARM diagnostic when 's' suffix on mnemonic that can't set flags.
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.

llvm-svn: 135203
2011-07-14 22:04:21 +00:00
Benjamin Kramer 3ceac21d37 Add OperandTypes for Thumb branch targets.
llvm-svn: 135199
2011-07-14 21:47:24 +00:00
Benjamin Kramer 9654eef493 Port operand types for ARM and X86 over from EDIS to the .td files.
llvm-svn: 135198
2011-07-14 21:47:22 +00:00
Jim Grosbach 26e7449443 ARM MCRR/MCRR2 immediate operand range checking.
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
Jim Grosbach d37d2025e9 ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
2011-07-14 21:19:17 +00:00
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
2011-07-14 20:59:42 +00:00
Jim Grosbach fa18793934 Reorganize ARM assembler aliases.
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.

llvm-svn: 135179
2011-07-14 19:47:47 +00:00
Benjamin Kramer 1757e7abeb Don't leak operands when putting them into a shift.
llvm-svn: 135169
2011-07-14 18:41:22 +00:00
Jim Grosbach 2f9aeeef3b Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
2011-07-14 18:35:38 +00:00
Jim Grosbach b218202586 ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
2011-07-14 18:00:31 +00:00
Jim Grosbach a0958d7abf ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
2011-07-14 00:18:13 +00:00
Jim Grosbach 56a20a492b DMB instalias needs the same predicate as the instruction.
llvm-svn: 135112
2011-07-14 00:10:26 +00:00
Jim Grosbach 44c3f08e85 ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
2011-07-13 23:40:38 +00:00
Jim Grosbach 199b683a6e Update comments. These are for assembler, too.
llvm-svn: 135107
2011-07-13 23:33:10 +00:00
Owen Anderson 651b230ca0 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Jim Grosbach 507ba77465 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
2011-07-13 22:59:38 +00:00
Jim Grosbach c5b4019a0d Revert 135093. Think-o.
llvm-svn: 135094
2011-07-13 22:06:11 +00:00
Jim Grosbach ccc207773d Correct range for thumb co-processor immediate
llvm-svn: 135093
2011-07-13 22:03:11 +00:00
Jim Grosbach 31756c2283 Range checking for CDP[2] immediates.
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Jim Grosbach ca7150b54d Cleanup Thumb co-processor instructions a bit.
Combine redundant base classes and such. No indended functional change.

llvm-svn: 135085
2011-07-13 21:35:10 +00:00
Jim Grosbach cabb48d511 Parameterize away the ARM T1Cop class.
llvm-svn: 135082
2011-07-13 21:17:59 +00:00
Jim Grosbach adb29b6dbb Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Jim Grosbach e2f9840cdb Fix encoding for ARM BXJ instruction.
llvm-svn: 135077
2011-07-13 20:25:01 +00:00
Jim Grosbach 801d3ad1b2 Fix encoding of predicate bits on ARM BX_pred.
llvm-svn: 135076
2011-07-13 20:21:31 +00:00
Jim Grosbach 975b641ee8 Range checking for 16-bit immediates in ARM assembly.
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Jim Grosbach e255be93a8 Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066
2011-07-13 19:24:09 +00:00
Jim Grosbach c845e55374 Add tests for ARM parsing of 'BKPT' instruction.
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach bb24c595f7 Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055
2011-07-13 18:49:30 +00:00
Jim Grosbach 04afb071e1 Destination register operand is optional for ADC and SBC ARM.
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach 7dcd1354f1 Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach 06210a28de 80 columns.
llvm-svn: 135047
2011-07-13 17:25:55 +00:00
Jim Grosbach 602aa90ab8 Update MCParsedAsmOperand debug methods.
Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.

llvm-svn: 135043
2011-07-13 15:34:57 +00:00
Evan Cheng 21e9051922 Add an entry.
llvm-svn: 135024
2011-07-13 01:33:00 +00:00
Evan Cheng f863e3fb73 Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317

llvm-svn: 135017
2011-07-13 00:42:17 +00:00
Jay Foad b804a2b751 Second attempt at de-constifying LLVM Types in FunctionType::get(),
StructType::get() and TargetData::getIntPtrType().

llvm-svn: 134982
2011-07-12 14:06:48 +00:00
Bill Wendling a78cd228c2 Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.

Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.

http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354

--- Reverse-merging r134893 into '.':
U    include/llvm/Target/TargetData.h
U    include/llvm/DerivedTypes.h
U    tools/bugpoint/ExtractFunction.cpp
U    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/ARM/ARMGlobalMerge.cpp
U    lib/Target/TargetData.cpp
U    lib/VMCore/Constants.cpp
U    lib/VMCore/Type.cpp
U    lib/VMCore/Core.cpp
U    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Instrumentation/ProfilingUtils.cpp
U    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G    include/llvm/DerivedTypes.h
U    include/llvm/Support/TypeBuilder.h
U    include/llvm/Intrinsics.h
U    unittests/Analysis/ScalarEvolutionTest.cpp
U    unittests/ExecutionEngine/JIT/JITTest.cpp
U    unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U    unittests/VMCore/PassManagerTest.cpp
G    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U    lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U    lib/VMCore/IRBuilder.cpp
G    lib/VMCore/Type.cpp
U    lib/VMCore/Function.cpp
G    lib/VMCore/Core.cpp
U    lib/VMCore/Module.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/Transforms/Utils/CloneFunction.cpp
G    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Utils/InlineFunction.cpp
U    lib/Transforms/Instrumentation/GCOVProfiling.cpp
U    lib/Transforms/Scalar/ObjCARC.cpp
U    lib/Transforms/Scalar/SimplifyLibCalls.cpp
U    lib/Transforms/Scalar/MemCpyOptimizer.cpp
G    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/Transforms/IPO/ArgumentPromotion.cpp
U    lib/Transforms/InstCombine/InstCombineCompares.cpp
U    lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U    lib/Transforms/InstCombine/InstCombineCalls.cpp
U    lib/CodeGen/DwarfEHPrepare.cpp
U    lib/CodeGen/IntrinsicLowering.cpp
U    lib/Bitcode/Reader/BitcodeReader.cpp

llvm-svn: 134949
2011-07-12 01:15:52 +00:00
Evan Cheng 58a98141d9 Most MCCodeEmitter's don't meed MCContext.
llvm-svn: 134922
2011-07-11 21:24:15 +00:00
Jim Grosbach a9a3f0a414 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

llvm-svn: 134903
2011-07-11 17:09:57 +00:00
Jim Grosbach 581da64241 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
2011-07-11 16:48:36 +00:00
Jay Foad 7c57be3e2b De-constify Types in StructType::get() and TargetData::getIntPtrType().
llvm-svn: 134893
2011-07-11 09:56:20 +00:00
Evan Cheng c5e6d2f519 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Cameron Zwarich 776403b642 Fix <rdar://problem/9751331>.
llvm-svn: 134882
2011-07-11 01:29:42 +00:00
Jakub Staszak 9b07c0ab6b Use BranchProbability instead of floating points in IfConverter.
llvm-svn: 134858
2011-07-10 02:58:07 +00:00
Evan Cheng 91111d2706 Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795
2011-07-09 05:47:46 +00:00
Evan Cheng 45543ba4e8 Fix indentation.
llvm-svn: 134764
2011-07-08 22:49:55 +00:00
Evan Cheng 284b467d9f Add support for ARM / Thumb mode switching with .code 16 and .code 32.
llvm-svn: 134760
2011-07-08 22:36:29 +00:00
Jim Grosbach 39c67b5e08 Mark tBRIND as predicable.
llvm-svn: 134758
2011-07-08 22:33:49 +00:00
Jim Grosbach 59a3ab6e46 Pseudo-ize tBRIND.
llvm-svn: 134755
2011-07-08 22:25:23 +00:00
Jim Grosbach 7471937ad7 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746
2011-07-08 21:50:04 +00:00
Cameron Zwarich f03fa189ca Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
2011-07-08 21:39:21 +00:00
Jim Grosbach d61ae786bd Pseudo-ize tBX_RET and tBX_RET_vararg.
llvm-svn: 134739
2011-07-08 21:10:35 +00:00
Benjamin Kramer debe69fb37 Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.
Found by valgrind.

llvm-svn: 134738
2011-07-08 21:06:23 +00:00
Jim Grosbach cb1b0b7130 Shuffle productions around a bit.
No functional change.

llvm-svn: 134737
2011-07-08 21:04:05 +00:00
Jim Grosbach 204c128f66 Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
llvm-svn: 134734
2011-07-08 20:39:19 +00:00
Jim Grosbach 4af8647e17 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
llvm-svn: 134732
2011-07-08 20:32:21 +00:00
Jim Grosbach 3840c90f73 Add more info to FIXME.
llvm-svn: 134729
2011-07-08 20:18:11 +00:00
Jim Grosbach 166cd88645 Move Thumb tail call pseudos to Thumb.td file.
Fix a FIXME.

llvm-svn: 134727
2011-07-08 20:13:35 +00:00
Evan Cheng 22e9d8f40e TargetAsmParser doesn't need reference to Target.
llvm-svn: 134721
2011-07-08 19:33:14 +00:00
Jim Grosbach dbfb29d6c0 Use ARMPseudoExpand for ARM tail calls.
llvm-svn: 134719
2011-07-08 18:50:22 +00:00
Jim Grosbach 7ddc1d709f Shuffle productions around a bit.
No functional change.

llvm-svn: 134714
2011-07-08 18:26:27 +00:00
Jim Grosbach 2dfe8e3ccd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712
2011-07-08 18:15:12 +00:00
Chandler Carruth f21cebf6dd Add CMake support for the new TableGen file introduced in r134705.
llvm-svn: 134707
2011-07-08 17:54:08 +00:00
Jim Grosbach 95dee40343 Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705
2011-07-08 17:40:42 +00:00
Evan Cheng 4d1ca96bfc Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
2011-07-08 01:53:10 +00:00
Evan Cheng 6dbe713a49 Rewrite comment in English.
llvm-svn: 134627
2011-07-07 19:09:06 +00:00
Evan Cheng 1834f5dcb6 Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
llvm-svn: 134626
2011-07-07 19:05:12 +00:00
Oscar Fuentes 32a45e5aeb Update CMake library dependencies
llvm-svn: 134616
2011-07-07 16:33:00 +00:00
Douglas Gregor cc4a55f6f2 Fix CMake build
llvm-svn: 134614
2011-07-07 15:59:22 +00:00
Cameron Zwarich 148220306f The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
2011-07-07 08:28:52 +00:00
Evan Cheng f2c2616e72 Sink feature IsThumb into MC layer.
llvm-svn: 134608
2011-07-07 08:26:46 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Evan Cheng 8b2bda09a5 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
llvm-svn: 134590
2011-07-07 03:55:05 +00:00
Evan Cheng 2bd65363a8 Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
llvm-svn: 134569
2011-07-07 00:08:19 +00:00
Evan Cheng 928ce72bcd Add ARM MC registry routines.
llvm-svn: 134547
2011-07-06 22:02:34 +00:00
Jim Grosbach 7c301ea093 Mark ARM pseudo-instructions as isPseudo.
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540
2011-07-06 21:35:46 +00:00
Jim Grosbach 4db363af7c Remove un-used encoding info from Pseudo MLAv5.
Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533
2011-07-06 20:57:35 +00:00
Evan Cheng ab37af9af3 createMCInstPrinter doesn't need TargetMachine anymore.
llvm-svn: 134525
2011-07-06 19:45:42 +00:00
Jim Grosbach ea53901dc9 ARM estimateStackSize() needs to account for simplified call frames.
If the function allocates reserved stack space for callee argument frames,
estimateStackSize() needs to account for that, as it doesn't show up as
ordinary frame objects. Otherwise, a callee with a large argument list will
throw off the calculations for whether to allocate an emergency spill slot
and we get assert() failures in the register scavenger.

rdar://9715469

llvm-svn: 134415
2011-07-05 16:05:50 +00:00
Evan Cheng c9c090d7a5 Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
llvm-svn: 134281
2011-07-01 22:36:09 +00:00
Jim Grosbach cf1464d943 ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992

llvm-svn: 134261
2011-07-01 21:12:19 +00:00
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency.
llvm-svn: 134259
2011-07-01 21:01:15 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
2011-07-01 20:45:01 +00:00
Jim Grosbach 68b0e8456e Fix off-by-one error.
(low two bits always zero, so off by one bit of encoded value).

llvm-svn: 134247
2011-07-01 19:07:09 +00:00
Evan Cheng 703a0fbf39 Hide the call to InitMCInstrInfo into tblgen generated ctor.
llvm-svn: 134244
2011-07-01 17:57:27 +00:00
Jim Grosbach 4def704a21 Pseudo-ize t2MOVCC[ri].
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.

llvm-svn: 134242
2011-07-01 17:14:11 +00:00