Commit Graph

5207 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 59015c8b17 Add <imp-def> operands to QQ and QQQQ stack loads.
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

llvm-svn: 138164
2011-08-20 00:17:45 +00:00
Chad Rosier be7625161e VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

llvm-svn: 138163
2011-08-20 00:17:25 +00:00
Jim Grosbach 2597722e07 Thumb parsing and encoding support for NOP.
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
2011-08-19 23:24:36 +00:00
Jim Grosbach 37aa348195 Thumb assembly parsing and encoding for NEG.
llvm-svn: 138131
2011-08-19 22:51:03 +00:00
Jim Grosbach 8022015a16 Fix NEG alias
llvm-svn: 138125
2011-08-19 22:30:58 +00:00
Jim Grosbach 459422d750 Be more lenient on tied operand matching for MUL.
llvm-svn: 138124
2011-08-19 22:30:46 +00:00
Jim Grosbach 066e9ec1e4 Update tests.
llvm-svn: 138116
2011-08-19 22:19:48 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL.
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV.
llvm-svn: 138076
2011-08-19 20:46:54 +00:00
Jim Grosbach dbb60f960a Tidy up. Tab character.
llvm-svn: 138072
2011-08-19 20:30:19 +00:00
Jim Grosbach 9c92049069 Tab characters.
llvm-svn: 138066
2011-08-19 19:41:46 +00:00
Jim Grosbach 5503c3a4e8 Thumb assembly parsing and encoding for LSL(immediate).
llvm-svn: 138063
2011-08-19 19:29:25 +00:00
Jim Grosbach 7c4739da3c Thumb assembly parsing and encoding for LDRSB and LDRSH.
llvm-svn: 138061
2011-08-19 19:17:58 +00:00
Jim Grosbach 26d3587bd8 Thumb assembly parsing and encoding for LDRH.
llvm-svn: 138060
2011-08-19 18:55:51 +00:00
Jim Grosbach a32c753ebf Thumb assembly parsing and encoding for LDRB.
llvm-svn: 138059
2011-08-19 18:49:59 +00:00
Jim Grosbach 181d2f92b5 Thumb assembly parsing and encoding for LDR(literal).
llvm-svn: 138052
2011-08-19 18:20:48 +00:00
Jim Grosbach 23983d6bd9 Thumb assembly parsing and encoding for LDR(immediate) form T2.
llvm-svn: 138050
2011-08-19 18:13:48 +00:00
Jim Grosbach 7473329725 Use helper function to check for low registers.
llvm-svn: 138048
2011-08-19 17:57:22 +00:00
Jim Grosbach 3fe94e3ef8 Thumb assembly parsing and encoding for LDR(immediate) form T1.
llvm-svn: 138047
2011-08-19 17:55:24 +00:00
Jim Grosbach e93807049b Add explanatory comment.
llvm-svn: 138042
2011-08-19 16:52:32 +00:00
Benjamin Kramer 4938edb02c Make a bunch of symbols private.
llvm-svn: 138025
2011-08-19 01:42:18 +00:00
Owen Anderson 96b7ad2e17 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.

llvm-svn: 138003
2011-08-18 22:47:44 +00:00
Owen Anderson 192a760b54 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
Owen Anderson 5d2db89ba6 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
llvm-svn: 137997
2011-08-18 22:15:25 +00:00
Owen Anderson 67d6f11974 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
2011-08-18 22:11:02 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
2011-08-18 21:50:53 +00:00
Jim Grosbach 4f240a1fd5 Thumb assembly parsing and encoding for CMP.
llvm-svn: 137963
2011-08-18 18:08:29 +00:00
Jim Grosbach 8a6bed863a Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
llvm-svn: 137956
2011-08-18 17:51:36 +00:00
Jim Grosbach f00b9ccd22 ARM Thumb blx instruction fixup has same data range as bl.
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.

llvm-svn: 137947
2011-08-18 16:57:50 +00:00
Jim Grosbach 8fa3f6a2b4 80 columns.
llvm-svn: 137946
2011-08-18 16:50:45 +00:00
Jim Grosbach 6ddb568ab8 Add missing 'break'.
llvm-svn: 137941
2011-08-18 16:08:39 +00:00
Jim Grosbach 50aafeaa2c Remove extraneous newline from operand print method. PR10569.
llvm-svn: 137900
2011-08-17 23:23:07 +00:00
Jim Grosbach 23b729eeba Clean up patterns for Thumb1 system instructions.
llvm-svn: 137897
2011-08-17 23:08:57 +00:00
Jim Grosbach cbd4ab104b Thumb assembly parsing and encoding for B.
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
Jim Grosbach d3e8e29124 Thumb assembly parsing and encoding for ASR.
llvm-svn: 137889
2011-08-17 22:49:09 +00:00
Jim Grosbach d14b70d00b Tidy up. 80 columns.
llvm-svn: 137881
2011-08-17 21:58:18 +00:00
Jim Grosbach 46dd413991 ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879
2011-08-17 21:51:27 +00:00
Jim Grosbach 854fe433d4 Fix predicate for imm1_32
llvm-svn: 137865
2011-08-17 21:01:11 +00:00
Jim Grosbach e2a0404a69 Thumb assembly parsing and encoding for ADR.
llvm-svn: 137864
2011-08-17 20:37:40 +00:00
Jim Grosbach 3b5a69cc45 80 columns.
llvm-svn: 137857
2011-08-17 19:55:51 +00:00
Jim Grosbach 8637523886 Tidy up.
llvm-svn: 137856
2011-08-17 19:53:53 +00:00
Owen Anderson 187e1e46f9 Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
llvm-svn: 137838
2011-08-17 18:14:48 +00:00
Owen Anderson a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830
2011-08-17 17:44:15 +00:00
Jim Grosbach e9ab47a72a Thumb ADD(immediate) parsing support.
llvm-svn: 137788
2011-08-16 23:57:34 +00:00
Owen Anderson 91a8f9be20 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
llvm-svn: 137787
2011-08-16 23:45:44 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
Jim Grosbach 64610e52e7 Add missing exit for 'case'.
llvm-svn: 137774
2011-08-16 21:42:31 +00:00
Jim Grosbach 58ffdccab1 Thumb assembly parsing and encoding for ADD(register) instruction.
llvm-svn: 137759
2011-08-16 21:34:08 +00:00
Jim Grosbach 7283da9bb2 Move some logic into a helper function and expand the commentary.
llvm-svn: 137756
2011-08-16 21:12:37 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions.
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
2011-08-16 20:45:50 +00:00
Jim Grosbach 45e50d8a0b ARM .align NOP padding uses different encoding pre-ARMv6.
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
2011-08-16 17:06:20 +00:00
Owen Anderson a6201f0a72 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
llvm-svn: 137686
2011-08-15 23:38:54 +00:00
Jim Grosbach 120a96a721 MCTargetAsmParser target match predicate support.
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675
2011-08-15 23:03:29 +00:00
Owen Anderson 1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.

llvm-svn: 137647
2011-08-15 20:51:32 +00:00
Owen Anderson de25f9aa8f Remove dead classes.
llvm-svn: 137643
2011-08-15 20:11:11 +00:00
Owen Anderson 61a3ece665 Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
Owen Anderson 3157f2eebe Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
Owen Anderson b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
Jim Grosbach 30694dcdeb Update comment to reflect MC target machine refactor.
llvm-svn: 137615
2011-08-15 16:52:24 +00:00
Bob Wilson d1de7764be Expand VMOVQQQQ pseudo instructions.
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551
2011-08-13 05:14:55 +00:00
Jim Grosbach 2325474368 ARM STR_POST_IMM offset encoding fix in load/store optimizer.
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.

rdar://9945172

llvm-svn: 137525
2011-08-12 22:20:41 +00:00
Jim Grosbach f402f694e2 ARM expansion of pre-indexed store pseudos should maintain memoperands.
Partial fix for rdar://9945172.

llvm-svn: 137513
2011-08-12 21:02:34 +00:00
Owen Anderson 2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
Owen Anderson 60138eaf93 Fix decoding of ARM-mode STRH.
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
Owen Anderson 1043e173bc Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
llvm-svn: 137494
2011-08-12 19:41:29 +00:00
Owen Anderson 3987a61c16 Fix decoding of pre-indexed stores.
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
Owen Anderson c5798a3a59 Separate decoding for STREXD and LDREXD to make each work better.
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
Duncan Sands a41634e307 Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.

llvm-svn: 137460
2011-08-12 14:54:45 +00:00
Jim Grosbach 8cffa28af8 ARM vector compare to zero instruction assembly parsing support.
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
Jim Grosbach 37f7e6b2f4 Remove no-longer-true comments. These are for the assembler, also.
llvm-svn: 137375
2011-08-11 22:30:30 +00:00
Jim Grosbach e25942154c ARM STRT assembly parsing and encoding.
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Owen Anderson eca346ee1a Make the USAT16 operand decoder auto-generate-able.
llvm-svn: 137371
2011-08-11 22:10:11 +00:00
Owen Anderson ff0b442330 Add another accidentally omitted predicate operand.
llvm-svn: 137370
2011-08-11 22:08:38 +00:00
Owen Anderson 2f7aa73312 Add missing predicate operand on SMLA and friends.
llvm-svn: 137368
2011-08-11 22:05:38 +00:00
Jim Grosbach a2b8b60646 ARM load shifted register pre-index fix shift value asm parser encoding.
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
Owen Anderson 12d13efa21 Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
llvm-svn: 137364
2011-08-11 21:52:38 +00:00
Owen Anderson f05e744857 Making SEL decodings auto-generate-able.
llvm-svn: 137363
2011-08-11 21:50:56 +00:00
Jim Grosbach 88981ff168 Tidy up comment.
llvm-svn: 137359
2011-08-11 21:41:59 +00:00
Owen Anderson b685c9f011 Fix decoding support for STREXD and LDREXD.
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding.
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
Owen Anderson 3a850f28d0 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
Jim Grosbach 2ea19d1438 Tidy up. Remove unused template parameter.
llvm-svn: 137345
2011-08-11 20:41:13 +00:00
Owen Anderson 887c0b1358 Improve operand validation for Thumb2 addressing modes.
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding.
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
Owen Anderson 6066340301 Continue to tighten decoding by performing more operand validation.
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach 1b0f79573e Tidy up.
llvm-svn: 137339
2011-08-11 20:13:35 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding.
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding.
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Owen Anderson 3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Owen Anderson ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy.
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Jim Grosbach d5d6359785 ARM LDRT assembly parsing and encoding.
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Jim Grosbach d3f7bcd43c Tidy up. 80 columns.
llvm-svn: 137277
2011-08-10 23:23:47 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support.
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Jim Grosbach f7164b2cfd Fix typo. Not quite sure how that slipped in there.
llvm-svn: 137245
2011-08-10 20:49:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support.
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Owen Anderson c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode.
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson 1531e5cd2b Tabs --> spaces.
llvm-svn: 137225
2011-08-10 17:38:05 +00:00
Owen Anderson 5d69f63bbb Cleanups based on Nick Lewycky's feedback.
llvm-svn: 137224
2011-08-10 17:36:48 +00:00
Owen Anderson 732f82c463 Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
llvm-svn: 137223
2011-08-10 17:21:20 +00:00
Rafael Espindola 36a3abc671 Add support for the R and Q constraints.
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
Owen Anderson 8059f0cf8d Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Jakob Stoklund Olesen 6a14dc01ff Promote VMOVS to VMOVD when possible.
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.

This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline.  Example:

        vldr.32 s0, LCPI0_0
    loop:
        vorr    d1, d0, d0
    loop2:
        ...
        vadd.f32        d1, d1, d16

The vorr instruction looked like this after regalloc:

    %S2<def> = COPY %S0, %D1<imp-def>

Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.

llvm-svn: 137182
2011-08-09 23:41:44 +00:00
Owen Anderson 92b942b1b5 Tighten operand checking of register-shifted-register operands.
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson e008931bf6 Tighten operand checking on memory barrier instructions.
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson 3d2e0e9db6 Tighten operand checking on CPS instructions.
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson 042619f97d Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Benjamin Kramer 406dc1755f ARM Disassembler: sign extend branch immediates.
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
2011-08-09 22:02:50 +00:00
Owen Anderson d151b09921 Silence an false-positive warning.
llvm-svn: 137154
2011-08-09 21:38:14 +00:00
Owen Anderson d770f6c110 Don't generate the old-style disassembler in CMake builds either.
llvm-svn: 137153
2011-08-09 21:36:11 +00:00
Benjamin Kramer de2c381331 The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
llvm-svn: 137151
2011-08-09 21:34:19 +00:00
Owen Anderson 982aa05017 Don't continue generating the old-style decoder file.
llvm-svn: 137150
2011-08-09 21:30:29 +00:00
Jim Grosbach 5e80abbb5d ARM fix typo in pre-indexed store lowering.
rdar://9915869

llvm-svn: 137148
2011-08-09 21:22:41 +00:00
Owen Anderson c7afd84322 Attempt to fix CMake build.
llvm-svn: 137147
2011-08-09 21:09:59 +00:00
Owen Anderson 7a2401dbf0 Tighten Thumb1 branch predicate decoding.
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
Owen Anderson e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Renato Golin faff512536 Emitting ARM build attributes and values as ULEB, rather than char.
llvm-svn: 137115
2011-08-09 09:50:10 +00:00
Jim Grosbach cab35c0836 ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
2011-08-08 23:28:47 +00:00
Owen Anderson 03ac20fc66 Thumb1 BL instructions encoding 22 bits of displacement, not 21.
llvm-svn: 137073
2011-08-08 23:25:22 +00:00
Jakob Stoklund Olesen c04a66b48e Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
They improve the verbose assembly.

llvm-svn: 137069
2011-08-08 21:45:32 +00:00
Jim Grosbach 95466ce63b ARM load/store label parsing.
Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.

llvm-svn: 137064
2011-08-08 20:59:31 +00:00
Owen Anderson c40303885b Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
llvm-svn: 137062
2011-08-08 20:42:17 +00:00
Eli Friedman a27da98921 Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
llvm-svn: 137061
2011-08-08 19:49:37 +00:00
Benjamin Kramer c22d50e5c3 Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

llvm-svn: 137059
2011-08-08 18:56:44 +00:00
Jim Grosbach 3d0b3a3a50 ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
2011-08-05 22:03:36 +00:00
Jim Grosbach c320c85261 ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
2011-08-05 21:28:30 +00:00
Jim Grosbach f0c95cadc7 ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.

llvm-svn: 136978
2011-08-05 20:35:44 +00:00
Jim Grosbach a70fbfd577 ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969
2011-08-05 16:11:38 +00:00
Jim Grosbach bafce840ff ARM use a dedicated printer for postidx_reg operands.
llvm-svn: 136968
2011-08-05 15:48:21 +00:00
Bob Wilson 8de11bab76 Add missing register constraint for some VLD3/VLD4 pseudo instructions.
<rdar://problem/9878189>

llvm-svn: 136962
2011-08-05 07:24:09 +00:00
Owen Anderson 08d4bb0f12 Fix broken encodings for the Thumb2 LDRD/STRD instructions.
llvm-svn: 136942
2011-08-04 23:18:05 +00:00
Jim Grosbach cd17c12078 ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.

llvm-svn: 136940
2011-08-04 23:01:30 +00:00
Owen Anderson ce5190321e LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
llvm-svn: 136896
2011-08-04 18:24:14 +00:00
Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Owen Anderson 7bc3b11a56 Fix broken encoding of tCBNZ.
llvm-svn: 136837
2011-08-03 23:21:48 +00:00
Eli Friedman 30a49e93e3 New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
2011-08-03 21:06:02 +00:00
Eli Friedman 5c863aeefd ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.
llvm-svn: 136737
2011-08-02 22:44:16 +00:00
Owen Anderson 713406f88d Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
llvm-svn: 136707
2011-08-02 18:30:00 +00:00
Jim Grosbach c8c63914c5 Tidy up. 80 columns.
llvm-svn: 136705
2011-08-02 18:16:36 +00:00
Jim Grosbach 9ec152b6bf ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704
2011-08-02 18:07:32 +00:00
Jim Grosbach 9f620a6883 Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
llvm-svn: 136656
2011-08-01 22:02:20 +00:00
Jim Grosbach 0f731b3232 Fix comments.
llvm-svn: 136655
2011-08-01 21:55:12 +00:00
Douglas Gregor d41f3a161f Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC.
llvm-svn: 136621
2011-08-01 16:29:27 +00:00
Eric Christopher aa5030066f Add support for the 'Q' constraint.
Fixes rdar://9866494

llvm-svn: 136523
2011-07-29 21:18:58 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach e537438ca5 ARM CPS mode immediate is 5 bits, not 4.
llvm-svn: 136505
2011-07-29 20:02:39 +00:00
Jim Grosbach c4dc52cd52 ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Jim Grosbach 20d38124a2 ARM SRS and RFE instructions are not code-gen only.
llvm-svn: 136475
2011-07-29 17:51:39 +00:00
Jim Grosbach 3b764cfd48 ARM range checking for mode on CPS instruction.
llvm-svn: 136473
2011-07-29 17:42:17 +00:00
Jim Grosbach e658f4faeb Update FIXME.
llvm-svn: 136470
2011-07-29 17:36:04 +00:00
Jim Grosbach 47859c8ab0 Tweak comment.
llvm-svn: 136468
2011-07-29 17:33:29 +00:00
Jakob Stoklund Olesen b28ee4115d Transfer implicit operands in NEONMoveFixPass.
Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

llvm-svn: 136440
2011-07-29 00:27:35 +00:00
Jakob Stoklund Olesen 9c3badceba Add -verify-arm-pseudo-expand.
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

llvm-svn: 136439
2011-07-29 00:27:32 +00:00
Chandler Carruth 9d7feab3e0 Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

llvm-svn: 136433
2011-07-29 00:14:25 +00:00
Jim Grosbach dd475c39d7 PLD and PLI are not predicable in ARM mode.
llvm-svn: 136427
2011-07-28 23:22:41 +00:00
Jim Grosbach a03ab0e3dc ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406
2011-07-28 21:57:55 +00:00
Jim Grosbach 864b609491 ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399
2011-07-28 21:34:26 +00:00
Jim Grosbach bfb439b140 Add fixme.
llvm-svn: 136375
2011-07-28 19:46:12 +00:00
Owen Anderson 7c965e7520 Update comments.
llvm-svn: 136367
2011-07-28 17:56:55 +00:00
Owen Anderson 301f793ed5 Fill in some encoding information for STRD instructions.
llvm-svn: 136366
2011-07-28 17:53:25 +00:00
Owen Anderson b0e6899398 Revert r136295. It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now.
llvm-svn: 136362
2011-07-28 17:18:57 +00:00
Jim Grosbach 8b3184e540 ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.

llvm-svn: 136360
2011-07-28 16:33:54 +00:00
Oscar Fuentes a8666a3cdb Explicitly declare a library dependency of LLVM*Desc to
LLVM*AsmPrinter.

GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:

../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'

llvm-svn: 136328
2011-07-28 02:33:52 +00:00
Owen Anderson b81af2abe0 Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.
llvm-svn: 136295
2011-07-27 23:36:57 +00:00
Evan Cheng eda1d4f3ba Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Jim Grosbach 57e2d3cb84 ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285
2011-07-27 22:34:17 +00:00
Eli Friedman 26a484852e Code generation for 'fence' instruction.
llvm-svn: 136283
2011-07-27 22:21:52 +00:00
Jim Grosbach 39b062bfaa ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277
2011-07-27 22:01:42 +00:00
Jim Grosbach 0c398b9c7e ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274
2011-07-27 21:58:11 +00:00
Jim Grosbach 03f56d9de6 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Owen Anderson fa9e6d43a0 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
llvm-svn: 136255
2011-07-27 20:29:48 +00:00
Jim Grosbach 833b9d3353 ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252
2011-07-27 20:15:40 +00:00
Jim Grosbach 66ee037863 ARM assembly parsing aliases for extend instructions w/o rotate.
llvm-svn: 136229
2011-07-27 18:19:32 +00:00
Jim Grosbach 38b5503d21 ARM cleanup of remaining extend instructions.
Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.

llvm-svn: 136226
2011-07-27 17:48:13 +00:00
Jim Grosbach 8b31ef50c0 ARM extend instructions simplification.
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.

llvm-svn: 136225
2011-07-27 16:47:19 +00:00
Evan Cheng 481ebb0133 Support .code32 and .code64 in X86 assembler.
llvm-svn: 136197
2011-07-27 00:38:12 +00:00
Jim Grosbach a5f7a8cfde ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.

llvm-svn: 136154
2011-07-26 21:44:37 +00:00
Jim Grosbach d2659138da ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152
2011-07-26 21:28:43 +00:00
Owen Anderson 2aedba6c5e Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
llvm-svn: 136141
2011-07-26 20:54:26 +00:00
Jim Grosbach 0d6022da6b Fix over-zealous rename from r136095.
llvm-svn: 136132
2011-07-26 20:41:24 +00:00
Jim Grosbach edaa35ae6f ARM diagnostics for ldrexd/stredx out of order paired register operands.
llvm-svn: 136110
2011-07-26 18:25:39 +00:00
Jim Grosbach cb31193670 ARM fix for LDREX source register encoding.
rdar://9842203

llvm-svn: 136102
2011-07-26 17:44:46 +00:00
Jim Grosbach 15e8d74231 ARM assembly parsing and encoding for SWP[B] instructions.
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
Jim Grosbach dbc1c5479e ARM SWP instructions store, too, not just load.
llvm-svn: 136096
2011-07-26 17:11:05 +00:00
Jim Grosbach eab1c0d09c Clean up the ARM asm parser a bit.
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.

llvm-svn: 136095
2011-07-26 17:10:22 +00:00
Jim Grosbach ddeda0fad3 ARM fix asm parsing range check for [0,31] immediates.
llvm-svn: 136091
2011-07-26 16:44:05 +00:00
Jim Grosbach f16378479b ARM parsing and encoding for SVC instruction.
llvm-svn: 136090
2011-07-26 16:24:27 +00:00
Evan Cheng 3a79225b4c Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
llvm-svn: 136031
2011-07-26 00:42:34 +00:00
Evan Cheng 1142444565 Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
llvm-svn: 136027
2011-07-26 00:24:13 +00:00
Chandler Carruth 97c069c1d2 Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

llvm-svn: 136023
2011-07-26 00:09:08 +00:00
Evan Cheng 5928e69d20 Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
llvm-svn: 136010
2011-07-25 23:24:55 +00:00
Jim Grosbach 475c6dbef6 ARM assembly parsing and encoding for SSAT16 instruction.
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
Jim Grosbach 3a9cbeed73 ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.

llvm-svn: 135990
2011-07-25 22:20:28 +00:00
Evan Cheng 9eec764c15 Fix more MC layering violations.
llvm-svn: 135979
2011-07-25 21:32:49 +00:00
Evan Cheng 61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration.
llvm-svn: 135974
2011-07-25 21:20:24 +00:00
Jim Grosbach 3ddf6aa503 Simply ARM so_reg MIOperandInfo definitions.
The shift immediate encoding, printing, etc. is handled directly by the
enclosing operand definition, so it should be a vanilla immediate, not a
nested complex operand (shift_imm).

llvm-svn: 135968
2011-07-25 21:04:58 +00:00
Evan Cheng f60768a14e Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore.
llvm-svn: 135963
2011-07-25 20:53:02 +00:00
Jim Grosbach ac798e1533 ARM asm operand renaming. Make things a bit more explicit.
llvm-svn: 135959
2011-07-25 20:49:51 +00:00
Jim Grosbach eeaab22166 More simple cleanup of ARM asm operand definitions.
llvm-svn: 135958
2011-07-25 20:38:18 +00:00
Evan Cheng f5bf19530b Code clean up.
llvm-svn: 135954
2011-07-25 20:18:48 +00:00
Jim Grosbach 2d6ef44d39 Make assembly parser method names more consistent.
llvm-svn: 135950
2011-07-25 20:14:50 +00:00
Jim Grosbach 46d575acc6 Tidy up formatting.
Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.

llvm-svn: 135946
2011-07-25 20:06:30 +00:00
Jim Grosbach 5ed9fe8037 Tidy up a bit.
llvm-svn: 135945
2011-07-25 20:00:32 +00:00
NAKAMURA Takumi 287bc6bdf6 ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.
llvm-svn: 135837
2011-07-23 01:16:22 +00:00
Evan Cheng f2596bc62a Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
llvm-svn: 135833
2011-07-23 00:45:41 +00:00
Evan Cheng ad5f485957 Sink ARM mc routines into MCTargetDesc.
llvm-svn: 135825
2011-07-23 00:00:19 +00:00
Jim Grosbach 801e0a3fde ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.

llvm-svn: 135823
2011-07-22 23:16:18 +00:00
Jim Grosbach e7e1e163db ARM assembly parsing and encoding updates.
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.

llvm-svn: 135817
2011-07-22 22:06:05 +00:00
Evan Cheng 8c886a40d2 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.

llvm-svn: 135812
2011-07-22 21:58:54 +00:00
Jim Grosbach 8dfcc0bb92 ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
2011-07-22 20:18:21 +00:00
Jim Grosbach d7c8c35301 ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.

llvm-svn: 135796
2011-07-22 20:11:20 +00:00
Owen Anderson 3fa7ca84d9 Fix test failures caused by my so_reg refactoring.
llvm-svn: 135785
2011-07-22 18:30:30 +00:00
Jim Grosbach d1f8bde10f ARM assembly parsing and encoding for SMC instruction.
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
Jim Grosbach bc9d841878 Clean up a few more comments.
These instruction definitions are for the assembler, too, not just the
disassembler.

llvm-svn: 135781
2011-07-22 18:06:01 +00:00
Jim Grosbach 163eb27c1a Tidy up.
llvm-svn: 135779
2011-07-22 18:04:10 +00:00
Jim Grosbach 39f9388a9d Thumb assembly support for SETEND instruction.
llvm-svn: 135778
2011-07-22 17:52:23 +00:00
Jim Grosbach 9afae0d01b Tidy up.
llvm-svn: 135777
2011-07-22 17:46:13 +00:00
Jim Grosbach 0a547701a4 ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.

llvm-svn: 135776
2011-07-22 17:44:50 +00:00
Jim Grosbach 41d084f807 Tidy up.
llvm-svn: 135771
2011-07-22 16:59:04 +00:00
Owen Anderson 0491270f99 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
Jim Grosbach 72e7c4f9ac ARM Asm parser range checking for [0,31] immediates.
llvm-svn: 135719
2011-07-21 23:26:25 +00:00
Jim Grosbach 2a0320c877 ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
2011-07-21 22:56:30 +00:00
Jim Grosbach 17806e6636 ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
2011-07-21 22:37:43 +00:00
Jim Grosbach 4aaae18d73 Tidy up.
llvm-svn: 135706
2011-07-21 21:26:05 +00:00
Jim Grosbach 0a8d89242f ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.

llvm-svn: 135702
2011-07-21 19:57:11 +00:00
Owen Anderson b595ed0085 Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
llvm-svn: 135693
2011-07-21 18:54:16 +00:00
Jim Grosbach 27c1e2560c ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
llvm-svn: 135682
2011-07-21 17:23:04 +00:00
Jay Foad ed8db7d9df Convert ConstantExpr::getGetElementPtr and
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.

llvm-svn: 135673
2011-07-21 14:31:17 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
Jim Grosbach a288b1c10a ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.

llvm-svn: 135626
2011-07-20 21:40:26 +00:00
Jim Grosbach 94df3be987 Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.

llvm-svn: 135617
2011-07-20 20:49:03 +00:00
Jim Grosbach a98f80095b ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.

llvm-svn: 135616
2011-07-20 20:32:09 +00:00
Jim Grosbach 8d11490771 ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596
2011-07-20 18:20:31 +00:00
Evan Cheng efd9b4240f - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
2011-07-20 07:51:56 +00:00
Evan Cheng 76792992d6 Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569
2011-07-20 05:58:47 +00:00
Jim Grosbach d25c2cdad7 Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
2011-07-19 22:45:10 +00:00
Jim Grosbach 97094d8f06 ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
2011-07-19 21:59:29 +00:00
Owen Anderson c78e03c39a Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
llvm-svn: 135524
2011-07-19 21:06:00 +00:00
Jim Grosbach 7d1e5f11ea ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521
2011-07-19 20:35:35 +00:00
Jim Grosbach 5cc3b4cd9a ARM assembly parsing for MOV (register).
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513
2011-07-19 20:10:31 +00:00
Jim Grosbach 81ebc733b4 Tidy up.
llvm-svn: 135507
2011-07-19 19:47:11 +00:00
Jim Grosbach 22ac078657 Tighten conditional for 'mov' cc_out.
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.

llvm-svn: 135506
2011-07-19 19:45:44 +00:00
Jim Grosbach 7c09e3c3f3 ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
2011-07-19 19:13:28 +00:00
Jim Grosbach b475205afd Remove unused code.
cc_out and pred operands are added during parsing via custom C++ now.

llvm-svn: 135497
2011-07-19 18:32:48 +00:00
Jim Grosbach 9720dcf70b ARM range checking for so_imm operands in assembly parsing.
llvm-svn: 135489
2011-07-19 16:50:30 +00:00
Evan Cheng 2129f59637 Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468
2011-07-19 06:37:02 +00:00