Commit Graph

5207 Commits

Author SHA1 Message Date
Andrew Trick 6446bf780a ARM fix for missing implicit operands on ldmia_ret.
rdar://10005094: miscompile of 176.gcc

llvm-svn: 138568
2011-08-25 17:50:53 +00:00
Andrew Trick f7ecc16c96 whitespace
llvm-svn: 138566
2011-08-25 17:40:54 +00:00
Jim Grosbach 1c171b121a Explicitly disallow predication in Thumb1 assembly.
llvm-svn: 138562
2011-08-25 17:23:55 +00:00
Evan Cheng 9dad430486 Hide -global-merge option.
llvm-svn: 138540
2011-08-25 01:22:49 +00:00
Evan Cheng f066b2fe99 Add a command line option to disable global merge pass.
llvm-svn: 138536
2011-08-25 01:00:36 +00:00
Evan Cheng 3ca20e64ac Remove a out-of-place comment.
llvm-svn: 138534
2011-08-25 00:54:42 +00:00
Owen Anderson 37612a3de3 Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
Jim Grosbach 21a60b6f90 ARM asm backend initialize isThumbMode based on target triple.
llvm-svn: 138501
2011-08-24 22:27:35 +00:00
Jim Grosbach 838ed3af46 Thumb .n mnemonic qualifiers can be ignored for now.
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.

llvm-svn: 138500
2011-08-24 22:19:48 +00:00
Jim Grosbach 4b701af908 Thumb parsing and encoding for SUB (SP minu immediate).
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494
2011-08-24 21:42:27 +00:00
Owen Anderson 216cfaa808 Be careful not to walk off the end of the operand info list while updating VFP predicates.
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
Jim Grosbach 0a0b3071df Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
2011-08-24 21:22:15 +00:00
Jim Grosbach af2f827a2c When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
rdar://10015134

llvm-svn: 138467
2011-08-24 20:06:14 +00:00
Jim Grosbach 6ccd79f4d5 Add missing explicit writeback operand to tSTMIA_UPD.
rdar://10014745

llvm-svn: 138457
2011-08-24 18:19:42 +00:00
Evan Cheng 2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.

llvm-svn: 138450
2011-08-24 18:08:43 +00:00
Jim Grosbach a281f2d07d Thumb add SP assembly syntax fix.
llvm-svn: 138448
2011-08-24 18:04:27 +00:00
Jim Grosbach 1b8457a84c Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.

llvm-svn: 138445
2011-08-24 17:46:13 +00:00
Owen Anderson 523004145e Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
Jim Grosbach 51b554247d Move ARM frame-unwinding EHABI handling a touch earlier.
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.

llvm-svn: 138386
2011-08-23 21:32:34 +00:00
Jim Grosbach 50b0f6669c [SU]XT[BH] are only available on ARMv6 and up.
llvm-svn: 138373
2011-08-23 20:53:08 +00:00
Evan Cheng 4d6c9d711d Some refactoring so TargetRegistry.h no longer has to include any files
from MC.

llvm-svn: 138367
2011-08-23 20:15:21 +00:00
Jim Grosbach 5cc338da67 Thumb parsing and encoding for SVC.
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
Jim Grosbach 505be75900 Thumb parsing and encoding for tSTRspi.
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
Jim Grosbach d80d169a04 Thumb parsing and encoding for STM.
llvm-svn: 138345
2011-08-23 18:15:37 +00:00
Jim Grosbach 169b2be611 Factor low reg checking into a helper function.
llvm-svn: 138344
2011-08-23 18:13:04 +00:00
Owen Anderson 924bcfc92f Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
Owen Anderson 9b7bd15d0b Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
llvm-svn: 138339
2011-08-23 17:45:18 +00:00
Jim Grosbach e364ad540a Clean up Thumb load/store multiple definitions.
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.

llvm-svn: 138338
2011-08-23 17:41:15 +00:00
Owen Anderson 041dba6dec Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
Jim Grosbach 3636be3c8f Thumb parsing and encoding for SBC.
llvm-svn: 138311
2011-08-22 23:55:58 +00:00
Jim Grosbach c3c32d9e09 Thumb parsing and encoding for RSB.
llvm-svn: 138308
2011-08-22 23:47:13 +00:00
Owen Anderson eb1367b2b8 Reject invalid imod values in t2CPS instructions.
llvm-svn: 138306
2011-08-22 23:44:04 +00:00
Owen Anderson 1346d79b4b t2SMLAD is a four-register instruction, not a three-register one.
llvm-svn: 138301
2011-08-22 23:31:45 +00:00
Owen Anderson f94b7b7d57 Correct operand naming of t2USAT16 to allow proper decoding.
llvm-svn: 138300
2011-08-22 23:27:47 +00:00
Jim Grosbach bfeb4f78af Revert r138278 now that r138289 has fixed the root issue.
llvm-svn: 138299
2011-08-22 23:25:48 +00:00
Owen Anderson 5e9989a920 Match operand naming to allow correct decoding of t2LDRSH_POST.
llvm-svn: 138298
2011-08-22 23:22:05 +00:00
Jim Grosbach 38c59fcb08 Improve error checking for tPUSH and tPOP register lists.
llvm-svn: 138295
2011-08-22 23:17:34 +00:00
Owen Anderson 2844a81079 Match operand names to provide correct decoding for Thumb2 SMULL.
llvm-svn: 138294
2011-08-22 23:16:48 +00:00
Owen Anderson a743409ec8 Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
llvm-svn: 138292
2011-08-22 23:10:16 +00:00
Jim Grosbach 139acd21e6 Thumb assemmbly parsing diagnostic improvements for LDM.
llvm-svn: 138287
2011-08-22 23:01:07 +00:00
Jim Grosbach ca2ffad8b1 Temporarilly mark tMUL as not commutable.
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.

llvm-svn: 138278
2011-08-22 22:00:18 +00:00
Owen Anderson 061738a680 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
llvm-svn: 138273
2011-08-22 21:34:00 +00:00
Owen Anderson df698b032c Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
Jim Grosbach 5c932b24be Tighten up ARM reglist validation a bit.
llvm-svn: 138258
2011-08-22 18:50:36 +00:00
Owen Anderson 721c3704da Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
Owen Anderson ac92e77bb8 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
Jim Grosbach 6caa557ae6 Clean up predicates on ARM target instruction aliases.
llvm-svn: 138249
2011-08-22 18:04:24 +00:00
Owen Anderson b49813206b Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
Chad Rosier 61f92efb5c Remove the VMOVQQ pseudo instruction.
llvm-svn: 138177
2011-08-20 00:52:40 +00:00
Chad Rosier baf5538da9 Remove VMOVQQQQ pseudo instruction.
llvm-svn: 138174
2011-08-20 00:40:14 +00:00
Jakob Stoklund Olesen 59015c8b17 Add <imp-def> operands to QQ and QQQQ stack loads.
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

llvm-svn: 138164
2011-08-20 00:17:45 +00:00
Chad Rosier be7625161e VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

llvm-svn: 138163
2011-08-20 00:17:25 +00:00
Jim Grosbach 2597722e07 Thumb parsing and encoding support for NOP.
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
2011-08-19 23:24:36 +00:00
Jim Grosbach 37aa348195 Thumb assembly parsing and encoding for NEG.
llvm-svn: 138131
2011-08-19 22:51:03 +00:00
Jim Grosbach 8022015a16 Fix NEG alias
llvm-svn: 138125
2011-08-19 22:30:58 +00:00
Jim Grosbach 459422d750 Be more lenient on tied operand matching for MUL.
llvm-svn: 138124
2011-08-19 22:30:46 +00:00
Jim Grosbach 066e9ec1e4 Update tests.
llvm-svn: 138116
2011-08-19 22:19:48 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL.
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV.
llvm-svn: 138076
2011-08-19 20:46:54 +00:00
Jim Grosbach dbb60f960a Tidy up. Tab character.
llvm-svn: 138072
2011-08-19 20:30:19 +00:00
Jim Grosbach 9c92049069 Tab characters.
llvm-svn: 138066
2011-08-19 19:41:46 +00:00
Jim Grosbach 5503c3a4e8 Thumb assembly parsing and encoding for LSL(immediate).
llvm-svn: 138063
2011-08-19 19:29:25 +00:00
Jim Grosbach 7c4739da3c Thumb assembly parsing and encoding for LDRSB and LDRSH.
llvm-svn: 138061
2011-08-19 19:17:58 +00:00
Jim Grosbach 26d3587bd8 Thumb assembly parsing and encoding for LDRH.
llvm-svn: 138060
2011-08-19 18:55:51 +00:00
Jim Grosbach a32c753ebf Thumb assembly parsing and encoding for LDRB.
llvm-svn: 138059
2011-08-19 18:49:59 +00:00
Jim Grosbach 181d2f92b5 Thumb assembly parsing and encoding for LDR(literal).
llvm-svn: 138052
2011-08-19 18:20:48 +00:00
Jim Grosbach 23983d6bd9 Thumb assembly parsing and encoding for LDR(immediate) form T2.
llvm-svn: 138050
2011-08-19 18:13:48 +00:00
Jim Grosbach 7473329725 Use helper function to check for low registers.
llvm-svn: 138048
2011-08-19 17:57:22 +00:00
Jim Grosbach 3fe94e3ef8 Thumb assembly parsing and encoding for LDR(immediate) form T1.
llvm-svn: 138047
2011-08-19 17:55:24 +00:00
Jim Grosbach e93807049b Add explanatory comment.
llvm-svn: 138042
2011-08-19 16:52:32 +00:00
Benjamin Kramer 4938edb02c Make a bunch of symbols private.
llvm-svn: 138025
2011-08-19 01:42:18 +00:00
Owen Anderson 96b7ad2e17 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.

llvm-svn: 138003
2011-08-18 22:47:44 +00:00
Owen Anderson 192a760b54 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
Owen Anderson 5d2db89ba6 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
llvm-svn: 137997
2011-08-18 22:15:25 +00:00
Owen Anderson 67d6f11974 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
2011-08-18 22:11:02 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
2011-08-18 21:50:53 +00:00
Jim Grosbach 4f240a1fd5 Thumb assembly parsing and encoding for CMP.
llvm-svn: 137963
2011-08-18 18:08:29 +00:00
Jim Grosbach 8a6bed863a Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
llvm-svn: 137956
2011-08-18 17:51:36 +00:00
Jim Grosbach f00b9ccd22 ARM Thumb blx instruction fixup has same data range as bl.
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.

llvm-svn: 137947
2011-08-18 16:57:50 +00:00
Jim Grosbach 8fa3f6a2b4 80 columns.
llvm-svn: 137946
2011-08-18 16:50:45 +00:00
Jim Grosbach 6ddb568ab8 Add missing 'break'.
llvm-svn: 137941
2011-08-18 16:08:39 +00:00
Jim Grosbach 50aafeaa2c Remove extraneous newline from operand print method. PR10569.
llvm-svn: 137900
2011-08-17 23:23:07 +00:00
Jim Grosbach 23b729eeba Clean up patterns for Thumb1 system instructions.
llvm-svn: 137897
2011-08-17 23:08:57 +00:00
Jim Grosbach cbd4ab104b Thumb assembly parsing and encoding for B.
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
Jim Grosbach d3e8e29124 Thumb assembly parsing and encoding for ASR.
llvm-svn: 137889
2011-08-17 22:49:09 +00:00
Jim Grosbach d14b70d00b Tidy up. 80 columns.
llvm-svn: 137881
2011-08-17 21:58:18 +00:00
Jim Grosbach 46dd413991 ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879
2011-08-17 21:51:27 +00:00
Jim Grosbach 854fe433d4 Fix predicate for imm1_32
llvm-svn: 137865
2011-08-17 21:01:11 +00:00
Jim Grosbach e2a0404a69 Thumb assembly parsing and encoding for ADR.
llvm-svn: 137864
2011-08-17 20:37:40 +00:00
Jim Grosbach 3b5a69cc45 80 columns.
llvm-svn: 137857
2011-08-17 19:55:51 +00:00
Jim Grosbach 8637523886 Tidy up.
llvm-svn: 137856
2011-08-17 19:53:53 +00:00
Owen Anderson 187e1e46f9 Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
llvm-svn: 137838
2011-08-17 18:14:48 +00:00
Owen Anderson a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830
2011-08-17 17:44:15 +00:00
Jim Grosbach e9ab47a72a Thumb ADD(immediate) parsing support.
llvm-svn: 137788
2011-08-16 23:57:34 +00:00
Owen Anderson 91a8f9be20 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
llvm-svn: 137787
2011-08-16 23:45:44 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
Jim Grosbach 64610e52e7 Add missing exit for 'case'.
llvm-svn: 137774
2011-08-16 21:42:31 +00:00
Jim Grosbach 58ffdccab1 Thumb assembly parsing and encoding for ADD(register) instruction.
llvm-svn: 137759
2011-08-16 21:34:08 +00:00
Jim Grosbach 7283da9bb2 Move some logic into a helper function and expand the commentary.
llvm-svn: 137756
2011-08-16 21:12:37 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions.
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
2011-08-16 20:45:50 +00:00
Jim Grosbach 45e50d8a0b ARM .align NOP padding uses different encoding pre-ARMv6.
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
2011-08-16 17:06:20 +00:00
Owen Anderson a6201f0a72 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
llvm-svn: 137686
2011-08-15 23:38:54 +00:00
Jim Grosbach 120a96a721 MCTargetAsmParser target match predicate support.
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675
2011-08-15 23:03:29 +00:00
Owen Anderson 1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.

llvm-svn: 137647
2011-08-15 20:51:32 +00:00
Owen Anderson de25f9aa8f Remove dead classes.
llvm-svn: 137643
2011-08-15 20:11:11 +00:00
Owen Anderson 61a3ece665 Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
Owen Anderson 3157f2eebe Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
Owen Anderson b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
Jim Grosbach 30694dcdeb Update comment to reflect MC target machine refactor.
llvm-svn: 137615
2011-08-15 16:52:24 +00:00
Bob Wilson d1de7764be Expand VMOVQQQQ pseudo instructions.
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551
2011-08-13 05:14:55 +00:00
Jim Grosbach 2325474368 ARM STR_POST_IMM offset encoding fix in load/store optimizer.
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.

rdar://9945172

llvm-svn: 137525
2011-08-12 22:20:41 +00:00
Jim Grosbach f402f694e2 ARM expansion of pre-indexed store pseudos should maintain memoperands.
Partial fix for rdar://9945172.

llvm-svn: 137513
2011-08-12 21:02:34 +00:00
Owen Anderson 2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
Owen Anderson 60138eaf93 Fix decoding of ARM-mode STRH.
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
Owen Anderson 1043e173bc Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
llvm-svn: 137494
2011-08-12 19:41:29 +00:00
Owen Anderson 3987a61c16 Fix decoding of pre-indexed stores.
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
Owen Anderson c5798a3a59 Separate decoding for STREXD and LDREXD to make each work better.
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
Duncan Sands a41634e307 Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.

llvm-svn: 137460
2011-08-12 14:54:45 +00:00
Jim Grosbach 8cffa28af8 ARM vector compare to zero instruction assembly parsing support.
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
Jim Grosbach 37f7e6b2f4 Remove no-longer-true comments. These are for the assembler, also.
llvm-svn: 137375
2011-08-11 22:30:30 +00:00
Jim Grosbach e25942154c ARM STRT assembly parsing and encoding.
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Owen Anderson eca346ee1a Make the USAT16 operand decoder auto-generate-able.
llvm-svn: 137371
2011-08-11 22:10:11 +00:00
Owen Anderson ff0b442330 Add another accidentally omitted predicate operand.
llvm-svn: 137370
2011-08-11 22:08:38 +00:00
Owen Anderson 2f7aa73312 Add missing predicate operand on SMLA and friends.
llvm-svn: 137368
2011-08-11 22:05:38 +00:00
Jim Grosbach a2b8b60646 ARM load shifted register pre-index fix shift value asm parser encoding.
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
Owen Anderson 12d13efa21 Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
llvm-svn: 137364
2011-08-11 21:52:38 +00:00
Owen Anderson f05e744857 Making SEL decodings auto-generate-able.
llvm-svn: 137363
2011-08-11 21:50:56 +00:00
Jim Grosbach 88981ff168 Tidy up comment.
llvm-svn: 137359
2011-08-11 21:41:59 +00:00
Owen Anderson b685c9f011 Fix decoding support for STREXD and LDREXD.
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding.
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
Owen Anderson 3a850f28d0 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
Jim Grosbach 2ea19d1438 Tidy up. Remove unused template parameter.
llvm-svn: 137345
2011-08-11 20:41:13 +00:00
Owen Anderson 887c0b1358 Improve operand validation for Thumb2 addressing modes.
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding.
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
Owen Anderson 6066340301 Continue to tighten decoding by performing more operand validation.
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach 1b0f79573e Tidy up.
llvm-svn: 137339
2011-08-11 20:13:35 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding.
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding.
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Owen Anderson 3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Owen Anderson ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy.
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Jim Grosbach d5d6359785 ARM LDRT assembly parsing and encoding.
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Jim Grosbach d3f7bcd43c Tidy up. 80 columns.
llvm-svn: 137277
2011-08-10 23:23:47 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support.
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Jim Grosbach f7164b2cfd Fix typo. Not quite sure how that slipped in there.
llvm-svn: 137245
2011-08-10 20:49:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support.
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Owen Anderson c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode.
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson 1531e5cd2b Tabs --> spaces.
llvm-svn: 137225
2011-08-10 17:38:05 +00:00
Owen Anderson 5d69f63bbb Cleanups based on Nick Lewycky's feedback.
llvm-svn: 137224
2011-08-10 17:36:48 +00:00
Owen Anderson 732f82c463 Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
llvm-svn: 137223
2011-08-10 17:21:20 +00:00
Rafael Espindola 36a3abc671 Add support for the R and Q constraints.
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
Owen Anderson 8059f0cf8d Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Jakob Stoklund Olesen 6a14dc01ff Promote VMOVS to VMOVD when possible.
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.

This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline.  Example:

        vldr.32 s0, LCPI0_0
    loop:
        vorr    d1, d0, d0
    loop2:
        ...
        vadd.f32        d1, d1, d16

The vorr instruction looked like this after regalloc:

    %S2<def> = COPY %S0, %D1<imp-def>

Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.

llvm-svn: 137182
2011-08-09 23:41:44 +00:00
Owen Anderson 92b942b1b5 Tighten operand checking of register-shifted-register operands.
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson e008931bf6 Tighten operand checking on memory barrier instructions.
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson 3d2e0e9db6 Tighten operand checking on CPS instructions.
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson 042619f97d Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Benjamin Kramer 406dc1755f ARM Disassembler: sign extend branch immediates.
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
2011-08-09 22:02:50 +00:00
Owen Anderson d151b09921 Silence an false-positive warning.
llvm-svn: 137154
2011-08-09 21:38:14 +00:00
Owen Anderson d770f6c110 Don't generate the old-style disassembler in CMake builds either.
llvm-svn: 137153
2011-08-09 21:36:11 +00:00
Benjamin Kramer de2c381331 The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
llvm-svn: 137151
2011-08-09 21:34:19 +00:00
Owen Anderson 982aa05017 Don't continue generating the old-style decoder file.
llvm-svn: 137150
2011-08-09 21:30:29 +00:00
Jim Grosbach 5e80abbb5d ARM fix typo in pre-indexed store lowering.
rdar://9915869

llvm-svn: 137148
2011-08-09 21:22:41 +00:00
Owen Anderson c7afd84322 Attempt to fix CMake build.
llvm-svn: 137147
2011-08-09 21:09:59 +00:00
Owen Anderson 7a2401dbf0 Tighten Thumb1 branch predicate decoding.
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
Owen Anderson e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Renato Golin faff512536 Emitting ARM build attributes and values as ULEB, rather than char.
llvm-svn: 137115
2011-08-09 09:50:10 +00:00
Jim Grosbach cab35c0836 ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
2011-08-08 23:28:47 +00:00
Owen Anderson 03ac20fc66 Thumb1 BL instructions encoding 22 bits of displacement, not 21.
llvm-svn: 137073
2011-08-08 23:25:22 +00:00
Jakob Stoklund Olesen c04a66b48e Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
They improve the verbose assembly.

llvm-svn: 137069
2011-08-08 21:45:32 +00:00
Jim Grosbach 95466ce63b ARM load/store label parsing.
Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.

llvm-svn: 137064
2011-08-08 20:59:31 +00:00
Owen Anderson c40303885b Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
llvm-svn: 137062
2011-08-08 20:42:17 +00:00
Eli Friedman a27da98921 Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
llvm-svn: 137061
2011-08-08 19:49:37 +00:00
Benjamin Kramer c22d50e5c3 Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

llvm-svn: 137059
2011-08-08 18:56:44 +00:00
Jim Grosbach 3d0b3a3a50 ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
2011-08-05 22:03:36 +00:00
Jim Grosbach c320c85261 ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
2011-08-05 21:28:30 +00:00
Jim Grosbach f0c95cadc7 ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.

llvm-svn: 136978
2011-08-05 20:35:44 +00:00
Jim Grosbach a70fbfd577 ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969
2011-08-05 16:11:38 +00:00
Jim Grosbach bafce840ff ARM use a dedicated printer for postidx_reg operands.
llvm-svn: 136968
2011-08-05 15:48:21 +00:00
Bob Wilson 8de11bab76 Add missing register constraint for some VLD3/VLD4 pseudo instructions.
<rdar://problem/9878189>

llvm-svn: 136962
2011-08-05 07:24:09 +00:00
Owen Anderson 08d4bb0f12 Fix broken encodings for the Thumb2 LDRD/STRD instructions.
llvm-svn: 136942
2011-08-04 23:18:05 +00:00
Jim Grosbach cd17c12078 ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.

llvm-svn: 136940
2011-08-04 23:01:30 +00:00
Owen Anderson ce5190321e LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
llvm-svn: 136896
2011-08-04 18:24:14 +00:00
Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Owen Anderson 7bc3b11a56 Fix broken encoding of tCBNZ.
llvm-svn: 136837
2011-08-03 23:21:48 +00:00
Eli Friedman 30a49e93e3 New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
2011-08-03 21:06:02 +00:00
Eli Friedman 5c863aeefd ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.
llvm-svn: 136737
2011-08-02 22:44:16 +00:00
Owen Anderson 713406f88d Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
llvm-svn: 136707
2011-08-02 18:30:00 +00:00
Jim Grosbach c8c63914c5 Tidy up. 80 columns.
llvm-svn: 136705
2011-08-02 18:16:36 +00:00
Jim Grosbach 9ec152b6bf ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704
2011-08-02 18:07:32 +00:00
Jim Grosbach 9f620a6883 Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
llvm-svn: 136656
2011-08-01 22:02:20 +00:00
Jim Grosbach 0f731b3232 Fix comments.
llvm-svn: 136655
2011-08-01 21:55:12 +00:00
Douglas Gregor d41f3a161f Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC.
llvm-svn: 136621
2011-08-01 16:29:27 +00:00
Eric Christopher aa5030066f Add support for the 'Q' constraint.
Fixes rdar://9866494

llvm-svn: 136523
2011-07-29 21:18:58 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach e537438ca5 ARM CPS mode immediate is 5 bits, not 4.
llvm-svn: 136505
2011-07-29 20:02:39 +00:00