95dee40343
Use TableGen'erated pseudo lowering for ARM.
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Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
llvm-svn: 134705
2011-07-08 17:40:42 +00:00
d23bfb8a7a
Make size computation less brittle.
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llvm-svn: 132222
2011-05-27 22:05:41 +00:00
3e021533cd
Teach dwarf writer to handle complex address expression for .debug_loc entries.
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This fixes clang generated blocks' variables' debug info.
Radar 9279956.
llvm-svn: 130373
2011-04-28 02:22:40 +00:00
e3745fdcf3
Revert r130178. It turned out to be not the optimal path to emit complex location expressions.
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llvm-svn: 130326
2011-04-27 20:29:27 +00:00
cae2fbd6fc
Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables.
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llvm-svn: 130178
2011-04-26 00:12:46 +00:00
3712c14be9
Fix DWARF description of S registers.
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llvm-svn: 129947
2011-04-21 22:48:26 +00:00
e7410dd0d5
Preliminary support for ARM frame save directives emission via MI flags.
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This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
llvm-svn: 127101
2011-03-05 18:43:32 +00:00
dfce83c8f5
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
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movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
llvm-svn: 123619
2011-01-17 08:03:18 +00:00
62acecd7e1
Model operand restrictions of mul-like instructions on ARMv5 via
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earlyclobber stuff. This should fix PRs 2313 and 8157.
Unfortunately, no testcase, since it'd be dependent on register
assignments.
llvm-svn: 122663
2011-01-01 20:38:38 +00:00
d0d1329fc8
Move the ARMAsmPrinter class defintiion into a header file.
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llvm-svn: 120551
2010-12-01 03:45:07 +00:00
Jim Grosbach