Commit Graph

311 Commits

Author SHA1 Message Date
Bill Schmidt 27917785ae Large code model support for PowerPC.
Large code model is identical to medium code model except that the
addis/addi sequence for "local" accesses is never used.  All accesses
use the addis/ld sequence.

The coding changes are straightforward; most of the patch is taken up
with creating variants of the medium model tests for large model.

llvm-svn: 175767
2013-02-21 17:12:27 +00:00
NAKAMURA Takumi 80159432de PPCDarwinAsmPrinter::EmitStartOfAsmFile(): Add checking range in CPUDirectives[].
llvm-svn: 174298
2013-02-04 00:47:38 +00:00
NAKAMURA Takumi 3d591ae0b9 PPCDarwinAsmPrinter::EmitStartOfAsmFile(): Add possible elements in CPUDirectives[].
llvm-svn: 174297
2013-02-04 00:47:33 +00:00
Adhemerval Zanella 1ae2248e14 PowerPC: EH adjustments
This patch adjust the r171506 to make all DWARF enconding pc-relative
for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT
(since the eh_frame will not generate PIC-relative relocation) and also
adds the emission of stubs created by the TTypeEncoding.

llvm-svn: 171979
2013-01-09 17:08:15 +00:00
Eric Christopher e3ab3d0e2c These functions have default arguments of 0 for the last arg. Use
them.

llvm-svn: 171933
2013-01-09 01:57:54 +00:00
Bill Schmidt 9b1e3e25dc This patch addresses bug 14678 by fixing two problems in medium code model
code generation.  Variables addressed through a GlobalAlias were not being
handled, and variables with available_externally linkage were treated
incorrectly.  The patch contains two new tests to verify the correct code
generation for these cases.

llvm-svn: 171778
2013-01-07 19:29:18 +00:00
Chandler Carruth 9fb823bbd4 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Bill Schmidt 9f0b4ec0f5 This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI.  The ABI will be updated with the new code sequence.

Former sequence:

  ld 9,x@got@tprel(2)
  add 9,9,x@tls

New sequence:

  addis 9,2,x@got@tprel@ha
  ld 9,x@got@tprel@l(9)
  add 9,9,x@tls

Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.

llvm-svn: 170209
2012-12-14 17:02:38 +00:00
Bill Schmidt 24b8dd6eb7 This patch implements local-dynamic TLS model support for the 64-bit
PowerPC target.  This is the last of the four models, so we now have 
full TLS support.

This is mostly a straightforward extension of the general dynamic model.
I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the
register copy following ADDI_TLSLD_L; otherwise everything above the
ADDIS_DTPREL_HA appeared dead and was removed.

As before, there are new test cases to test the assembly generation, and
the relocations output during integrated assembly.  The expected code
gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll.

There are a couple of things I think can be done more efficiently in the
overall TLS code, so there will likely be a clean-up patch forthcoming;
but for now I want to be sure the functionality is in place.

Bill

llvm-svn: 170003
2012-12-12 19:29:35 +00:00
Bill Schmidt c56f1d34bc This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:

     Instruction                            Relocation            Symbol
  addis ra,r2,x@got@tlsgd@ha           R_PPC64_GOT_TLSGD16_HA       x
  addi  r3,ra,x@got@tlsgd@l            R_PPC64_GOT_TLSGD16_L        x
  bl __tls_get_addr(x@tlsgd)           R_PPC64_TLSGD                x
                                       R_PPC64_REL24           __tls_get_addr
  nop
  <use address in r3>

The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation.  This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr.  Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation.  So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.

Most of the code is pretty straightforward.  I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call.  Something in the 
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations.  This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().

Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.

Comments welcome!

Thanks,
Bill

llvm-svn: 169910
2012-12-11 20:30:11 +00:00
Bill Schmidt ca4a0c9dbd This patch introduces initial-exec model support for thread-local storage
on 64-bit PowerPC ELF.

The patch includes code to handle external assembly and MC output with the
integrated assembler.  It intentionally does not support the "old" JIT.

For the initial-exec TLS model, the ABI requires the following to calculate
the address of external thread-local variable x:

 Code sequence            Relocation                  Symbol
  ld 9,x@got@tprel(2)      R_PPC64_GOT_TPREL16_DS      x
  add 9,9,x@tls            R_PPC64_TLS                 x

The register 9 is arbitrary here.  The linker will replace x@got@tprel
with the offset relative to the thread pointer to the generated GOT
entry for symbol x.  It will replace x@tls with the thread-pointer
register (13).

The two test cases verify correct assembly output and relocation output
as just described.

PowerPC-specific selection node variants are added for the two
instructions above:  LD_GOT_TPREL and ADD_TLS.  These are inserted
when an initial-exec global variable is encountered by
PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to
machine instructions LDgotTPREL and ADD8TLS.  LDgotTPREL is a pseudo
that uses the same LDrs support added for medium code model's LDtocL,
with a different relocation type.

The rest of the processing is straightforward.

llvm-svn: 169281
2012-12-04 16:18:08 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Bill Schmidt 34627e3434 This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer.  Additionally,
only TOC entries are addressed via the TOC pointer.

With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset.  Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed.  Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.

Consider a load of an external 4-byte integer.  With small code model, the
compiler generates:

	ld 3, .LC1@toc(2)
	lwz 4, 0(3)

	.section	.toc,"aw",@progbits
.LC1:
	.tc ei[TC],ei

With medium model, it instead generates:

	addis 3, 2, .LC1@toc@ha
	ld 3, .LC1@toc@l(3)
	lwz 4, 0(3)

	.section	.toc,"aw",@progbits
.LC1:
	.tc ei[TC],ei

Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer.  Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits.  Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.

Consider next a load of a function-scope static integer.  For small code
model, the compiler generates:

	ld 3, .LC1@toc(2)
	lwz 4, 0(3)

	.section	.toc,"aw",@progbits
.LC1:
	.tc test_fn_static.si[TC],test_fn_static.si
	.type	test_fn_static.si,@object
	.local	test_fn_static.si
	.comm	test_fn_static.si,4,4

For medium code model, the compiler generates:

	addis 3, 2, test_fn_static.si@toc@ha
	addi 3, 3, test_fn_static.si@toc@l
	lwz 4, 0(3)

	.type	test_fn_static.si,@object
	.local	test_fn_static.si
	.comm	test_fn_static.si,4,4

Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.

Note that it would be more efficient for the compiler to generate:

	addis 3, 2, test_fn_static.si@toc@ha
        lwz 4, test_fn_static.si@toc@l(3)

The current patch does not perform this optimization yet.  This will be
addressed as a peephole optimization in a later patch.

For the moment, the default code model for 64-bit PowerPC will remain the
small code model.  We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior.  Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.

I've tested the regression suite and the application/benchmark test suite in
two ways:  Once with the patch as submitted here, and once with additional
logic to force medium code model as the default.  The tests all compile
cleanly, with one exception.  The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers.  It just so happens
that small code model was incredibly lucky, in that temporary values in 
floating-point registers held the expected values needed by the external
library routine that was called incorrectly.  My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."

Here are a few comments on how the patch works, since the selection code
can be difficult to follow:

The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses.  These are expanded by SelectCodeCommon().  The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL.  These new node types correspond naturally to
the sequences described above.

The addis/ld sequence is generated for the following cases:
 * Jump table addresses
 * Function addresses
 * External global variables
 * Tentative definitions of global variables (common linkage)

The addis/addi sequence is generated for the following cases:
 * Constant pool entries
 * File-scope static global variables
 * Function-scope static variables

Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.

The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction.  Each of the instructions is converted to
a "real" PowerPC instruction.  When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).

I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a 
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL.  So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.

Note that for LDtocL, we generate a new form of LD called LDrs.  This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.

The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.

The above assumes use of an external assembler.  For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter.  Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.

llvm-svn: 168708
2012-11-27 17:35:46 +00:00
Benjamin Kramer ebf576d31d Decouple MCInstBuilder from the streamer per Eli's request.
llvm-svn: 168597
2012-11-26 18:05:52 +00:00
Benjamin Kramer 4e629f7964 Add MCInstBuilder, a utility class to simplify MCInst creation similar to MachineInstrBuilder.
Simplify some repetitive code with it. No functionality change.

llvm-svn: 168587
2012-11-26 13:34:22 +00:00
Benjamin Kramer dd76a93af5 PPC: MCize most of the darwin PIC emission.
The last remaining bit is "bcl 20, 31, AnonSymbol", which I couldn't find the
instruction definition for. Only whitespace changes in assembly output.

llvm-svn: 168541
2012-11-24 13:18:25 +00:00
Benjamin Kramer 69dc3fe461 PPC: Simplify code with Twines.
No functionality change.

llvm-svn: 168539
2012-11-24 13:18:11 +00:00
Ulrich Weigand 2c93acdfbf Make TOC order deterministic by using MapVector instead of DenseMap.
llvm-svn: 167737
2012-11-12 19:13:24 +00:00
Hal Finkel 4f24c621d9 Add support for the PowerPC-specific inline asm Z constraint and y modifier.
The Z constraint specifies an r+r memory address, and the y modifier expands
to the "r, r" in the asm string. For this initial implementation, the base
register is forced to r0 (which has the special meaning of 0 for r+r addressing
on PowerPC) and the full address is taken in the second register. In the
future, this should be improved.

llvm-svn: 167388
2012-11-05 18:18:42 +00:00
Chandler Carruth 5da3f0512e Revert the majority of the next patch in the address space series:
r165941: Resubmit the changes to llvm core to update the functions to
         support different pointer sizes on a per address space basis.

Despite this commit log, this change primarily changed stuff outside of
VMCore, and those changes do not carry any tests for correctness (or
even plausibility), and we have consistently found questionable or flat
out incorrect cases in these changes. Most of them are probably correct,
but we need to devise a system that makes it more clear when we have
handled the address space concerns correctly, and ideally each pass that
gets updated would receive an accompanying test case that exercises that
pass specificaly w.r.t. alternate address spaces.

However, from this commit, I have retained the new C API entry points.
Those were an orthogonal change that probably should have been split
apart, but they seem entirely good.

In several places the changes were very obvious cleanups with no actual
multiple address space code added; these I have not reverted when
I spotted them.

In a few other places there were merge conflicts due to a cleaner
solution being implemented later, often not using address spaces at all.
In those cases, I've preserved the new code which isn't address space
dependent.

This is part of my ongoing effort to clean out the partial address space
code which carries high risk and low test coverage, and not likely to be
finished before the 3.2 release looms closer. Duncan and I would both
like to see the above issues addressed before we return to these
changes.

llvm-svn: 167222
2012-11-01 09:14:31 +00:00
Adhemerval Zanella f2aceda854 Initial TOC support for PowerPC64 object creation
This patch adds initial PPC64 TOC MC object creation using the small mcmodel
(a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC,
R_PPC64_TOC16, and R_PPC64_TOC16DS).

The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter'
is meant to avoid the creation of an unreferenced ".TOC." symbol (used in
the .odp creation) as well to set the R_PPC64_TOC relocation target as the
temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should
not point to any symbol.

llvm-svn: 166677
2012-10-25 12:27:42 +00:00
Micah Villmow 4bb926d91d Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
llvm-svn: 165941
2012-10-15 16:24:29 +00:00
Adhemerval Zanella ef206f19a4 PowerPC: add EmitTCEntry class for TOC creation
This patch replaces the EmitRawText by a EmitTCEntry class (specialized for
each Streamer) in PowerPC64 TOC entry creation.

llvm-svn: 165940
2012-10-15 15:43:14 +00:00
Micah Villmow 0c61134d8d Revert 165732 for further review.
llvm-svn: 165747
2012-10-11 21:27:41 +00:00
Micah Villmow 083189730e Add in the first iteration of support for llvm/clang/lldb to allow variable per address space pointer sizes to be optimized correctly.
llvm-svn: 165726
2012-10-11 17:21:41 +00:00
Micah Villmow cdfe20b97f Move TargetData to DataLayout.
llvm-svn: 165402
2012-10-08 16:38:25 +00:00
Roman Divacky 0be33598ce Avoid symbol name clash when filling TOC.
Patch by Adhemerval Zanella.

llvm-svn: 164141
2012-09-18 17:10:37 +00:00
Roman Divacky d4f6f421a9 On PPC64 emit the environment pointer. Patch by Adhemerval Zanella.
llvm-svn: 164139
2012-09-18 16:55:29 +00:00
Roman Divacky 2be394bdcd Remove always true checks. Noticed by Adhemerval Zanella.
llvm-svn: 163117
2012-09-03 16:55:42 +00:00
Hal Finkel 1859d26528 Reserve space for the mandatory traceback fields on PPC64.
We need to reserve space for the mandatory traceback fields,
though leaving them as zero is appropriate for now.

Although the ABI calls for these fields to be filled in fully, no
compiler on Linux currently does this, and GDB does not read these
fields.  GDB uses the first word of zeroes during exception handling to
find the end of the function and the size field, allowing it to compute
the beginning of the function.  DWARF information is used for everything
else.  We need the extra 8 bytes of pad so the size field is found in
the right place.

As a comparison, GCC fills in a few of the fields -- language, number
of saved registers -- but ignores the rest.  IBM's proprietary OSes do
make use of the full traceback table facility.

Patch by Bill Schmidt.

llvm-svn: 162854
2012-08-29 20:22:24 +00:00
Roman Divacky 8c4b6a307e Emit word of zeroes after the last instruction as a start of the mandatory
traceback table on PowerPC64. This helps gdb handle exceptions. The other
mandatory fields are ignored by gdb and harder to implement so just add
there a FIXME.

Patch by Bill Schmidt. PR13641.

llvm-svn: 162778
2012-08-28 19:06:55 +00:00
Hal Finkel 742b535e40 Add PPC Freescale e500mc and e5500 subtargets.
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.

Patch by Tobias von Koch.

llvm-svn: 162764
2012-08-28 16:12:39 +00:00
Roman Divacky ace4707ea6 Lower constant pools and jump tables via TOC on PPC64/SVR4.
In collaboration with Adhemerval Zanella.

llvm-svn: 162562
2012-08-24 16:26:02 +00:00
Bill Wendling e38859dc8e Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.

The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.

llvm-svn: 159312
2012-06-28 00:05:13 +00:00
Jack Carter 5e69cffed5 There are a number of generic inline asm operand modifiers that
up to r158925 were handled as processor specific. Making them 
generic and putting tests for these modifiers in the CodeGen/Generic
directory caused a number of targets to fail. 

This commit addresses that problem by having the targets call 
the generic routine for generic modifiers that they don't currently
have explicit code for.

For now only generic print operands 'c' and 'n' are supported.vi


Affected files:

    test/CodeGen/Generic/asm-large-immediate.ll
    lib/Target/PowerPC/PPCAsmPrinter.cpp
    lib/Target/NVPTX/NVPTXAsmPrinter.cpp
    lib/Target/ARM/ARMAsmPrinter.cpp
    lib/Target/XCore/XCoreAsmPrinter.cpp
    lib/Target/X86/X86AsmPrinter.cpp
    lib/Target/Hexagon/HexagonAsmPrinter.cpp
    lib/Target/CellSPU/SPUAsmPrinter.cpp
    lib/Target/Sparc/SparcAsmPrinter.cpp
    lib/Target/MBlaze/MBlazeAsmPrinter.cpp
    lib/Target/Mips/MipsAsmPrinter.cpp
    
MSP430 isn't represented because it did not even run with
the long existing 'c' modifier and it was not apparent what
needs to be done to get it inline asm ready.

Contributer: Jack Carter
llvm-svn: 159203
2012-06-26 13:49:27 +00:00
Hal Finkel bfd3d08d18 Rename the PPC target feature gpul to mfocrf.
The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.

No functionality change.

llvm-svn: 158323
2012-06-11 19:57:01 +00:00
Hal Finkel f2b9c38d6f Add POWER6 and POWER7 CPU types to the PPC backend.
No functional change; these will be used by upcoming scheduler enhancements.

llvm-svn: 158313
2012-06-11 15:43:08 +00:00
Hal Finkel 9f9f8929ee Add instruction itinerary for the PPC64 A2 core.
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

llvm-svn: 153842
2012-04-01 19:22:40 +00:00
Craig Topper b25fda95f6 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
llvm-svn: 152997
2012-03-17 18:46:09 +00:00
Roman Divacky 34d4b9682b Properly MCize the section switch, removing a FIXME.
llvm-svn: 151639
2012-02-28 18:15:25 +00:00
Roman Divacky 8fe40cd659 Reapply r151278 with fixes.
MCize function entry label emission on PowerPC64 properly.

llvm-svn: 151547
2012-02-27 20:20:47 +00:00
Hal Finkel 6fd2b434bd Revert r151278, breaks static linking.
Reverting this because it breaks static linking on ppc64. Specifically, it may be linkonce_odr functions that are the problem.
With this patch, if you link statically, calls to some functions end up calling their descriptor addresses instead
of calling to their entry points. This causes the execution to fail with SIGILL (b/c the descriptor address just
has some pointers, not code).

llvm-svn: 151433
2012-02-25 03:40:11 +00:00
Roman Divacky a2d3608f78 MCize function entry label emission on PowerPC64 properly.
llvm-svn: 151278
2012-02-23 20:28:39 +00:00
Hal Finkel ad4d9f5848 Allow the use of an alternate symbol for calculating a function's size.
The standard function epilog includes a .size directive, but ppc64 uses
an alternate local symbol to tag the actual start of each function.

Until recently, binutils accepted the .size directive as:
 .size	test1, .Ltmp0-test1
however, using this directive with recent binutils will result in the error:
 .size expression for XXX does not evaluate to a constant
so we must use the label which actually tags the start of the function.

llvm-svn: 151200
2012-02-22 21:11:47 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Hal Finkel ac9df3d411 make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
llvm-svn: 146024
2011-12-07 06:34:06 +00:00
Eli Friedman c1870b2633 Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
llvm-svn: 145553
2011-12-01 01:43:47 +00:00
Devang Patel 2f70bcdb94 Remove unnecessary include.
llvm-svn: 144211
2011-11-09 21:11:02 +00:00
Hal Finkel 6fa5697af0 Add PPC 440 scheduler and some associated tests
llvm-svn: 142170
2011-10-17 04:03:49 +00:00
Evan Cheng 2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.

llvm-svn: 138450
2011-08-24 18:08:43 +00:00
Evan Cheng 1142444565 Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
llvm-svn: 136027
2011-07-26 00:24:13 +00:00
Evan Cheng 61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration.
llvm-svn: 135974
2011-07-25 21:20:24 +00:00
Evan Cheng ab37af9af3 createMCInstPrinter doesn't need TargetMachine anymore.
llvm-svn: 134525
2011-07-06 19:45:42 +00:00
Roman Divacky 4b5665a1f7 Fix emission of PPC64 assembler on non-darwin platforms by splitting
VK_PPC_{HA,LO}16 into darwin and gas variants.

Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.

llvm-svn: 132802
2011-06-09 20:25:38 +00:00
Bill Wendling 00f0cddfd4 We need to pass the TargetMachine object to the InstPrinter if we are printing
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.

This is part of a work-in-progress.

llvm-svn: 127986
2011-03-21 04:13:46 +00:00
Chris Lattner aac9fa731d Wire up primitive support in the assembler backend for writing .o files
directly on the mac.  This is very early, doesn't support relocations and
has a terrible hack to avoid .machine from being printed, but despite
that it generates an bitwise-identical-to-cctools .o file for stuff like 
this:

  define i32 @test() nounwind { ret i32 42 }

I don't plan to continue pushing this forward, but if anyone else was
interested in doing it, it should be really straight-forward.

llvm-svn: 119136
2010-11-15 08:49:58 +00:00
Chris Lattner 15e9d5ef8a fix a regression with the new instprinter: we lost the ability to
print DBG_VALUE instructions.  This should unbreak the llvm-gcc-powerpc-darwin9
buildbot.

llvm-svn: 119132
2010-11-15 07:52:06 +00:00
Chris Lattner 8bcfdab194 strength reduce TOC temp label generation, no functionality change.
llvm-svn: 119112
2010-11-15 03:42:54 +00:00
Chris Lattner 510c66f549 rip out a ton of old instruction printing junk now that the
new instprinting logic is there.

llvm-svn: 119111
2010-11-15 03:39:06 +00:00
Chris Lattner d7c2fc7a73 Turn on the new instprinter by default.
The only change in the output is:

1) we get a better comment on mfcr, we get:
	mfcr r2                         ; cr2
  instead of:
 	mfcr r2 ; 32

2) we no longer emit $stub's on powerpc/leopard.  The Leopard
   linker autosynthesizes them.

llvm-svn: 119108
2010-11-15 03:27:05 +00:00
Chris Lattner e75bb34963 remove some extraneous quotes to make the new instprinter match.
llvm-svn: 119104
2010-11-15 02:43:46 +00:00
Chris Lattner b7c67f6c17 with the picbase nonsense starting to be figured out, implement
lowering support for MovePCtoLR[8].  Down to 4 failures again.

llvm-svn: 119090
2010-11-14 22:56:43 +00:00
Chris Lattner 7077efe894 move the pic base symbol stuff up to MachineFunction
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.

llvm-svn: 119089
2010-11-14 22:48:15 +00:00
Chris Lattner 94f0c14cb0 reimplement ppc asmprinter "toc" handling to use a VariantKind
on the operand, required for .o file writing and fixing 
the PowerPC/mult-alt-generic-powerpc64.ll failure with the new
instprinter.

llvm-svn: 119087
2010-11-14 22:22:59 +00:00
Chris Lattner 2f9f63af0b lower PPC::MFCRpseud when transforming to MC, avoiding calling
the aborting printSpecial() method.  This gets us to 8 failures.

llvm-svn: 119084
2010-11-14 22:03:15 +00:00
Chris Lattner e2d75bf681 properly wire up the instprinter to the ppc64 backend, down to 5 failures.
llvm-svn: 119081
2010-11-14 21:42:53 +00:00
Chris Lattner 5c1b0cdec2 switch PPC to a simplified MCInstLowering model.
llvm-svn: 119074
2010-11-14 21:12:33 +00:00
Chris Lattner 7a5c57ecf4 Implement support for printing register and immediate operands,
add support for darwin vs aix syntax.  We now can print instructions
like this:

	add r3, r3, r4
	blr 

and (in aix mode):
	add 3, 3, 4
	blr 

llvm-svn: 119062
2010-11-14 20:02:39 +00:00
Chris Lattner 686a095d89 stub out PPCMCInstLowering, add a new option that uses it and the new
instprinter when -enable-ppc-inst-printer is passed to llc.

llvm-svn: 119061
2010-11-14 19:53:02 +00:00
Chris Lattner a76eab433a stub out a powerpc MCInstPrinter implementation.
llvm-svn: 119059
2010-11-14 19:40:38 +00:00
Chris Lattner 56477d1690 move PPCAsmPrinter into the main PPC library, like ARM and X86.
llvm-svn: 119054
2010-11-14 18:33:33 +00:00
Anton Korobeynikov 28dc9d0ad9 Factor out asmprinter out of ppc
llvm-svn: 54887
2008-08-17 13:54:28 +00:00
Anton Korobeynikov ed47329174 Handle visibility printing with all generality. Remove bunch of duplicate code.
llvm-svn: 54540
2008-08-08 18:25:07 +00:00
Anton Korobeynikov f1f8aa3e50 Use chars, where possible
llvm-svn: 54539
2008-08-08 18:24:10 +00:00
Anton Korobeynikov c9ad17c3da Convert PPC/Linux to new section printing stuff
llvm-svn: 54538
2008-08-08 18:23:49 +00:00
Anton Korobeynikov 5b5d8bcd88 Switch PPC/Darwin to new section handling stuff
llvm-svn: 54537
2008-08-08 18:23:25 +00:00
Anton Korobeynikov 7c20ede085 Cleanup
llvm-svn: 54536
2008-08-08 18:22:59 +00:00
Dale Johannesen ca43dce1e8 Remove extra call to DW.SetModuleInfo on Linux.
llvm-svn: 53365
2008-07-09 21:33:15 +00:00
Dale Johannesen dbd04c0783 Emit debug into for data-only files for Linux PPC.
I cannot test this target, let me know if it breaks!

llvm-svn: 53362
2008-07-09 21:24:07 +00:00
Dale Johannesen b9aaddc110 Emit debug info for data-only files. This version
applies to ppc Darwin only.

llvm-svn: 53353
2008-07-09 20:43:39 +00:00
Evan Cheng 49c8e68e4c Back out 53254. It broke ppc debug info codegen.
llvm-svn: 53280
2008-07-09 06:36:53 +00:00
Dale Johannesen b9097a71d4 Make debug info come out in data-only files.
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason.  I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.

llvm-svn: 53254
2008-07-08 21:56:22 +00:00
Dale Johannesen 18cc4d3ea4 Put initialized const weak objects into correct
sections on ppc32 darwin.  g++.dg/abi/key2.C

llvm-svn: 51527
2008-05-24 00:10:20 +00:00
Dale Johannesen 5bf742f2aa Handle quoted names when constructing $stub's,
$non_lazy_ptr's and $lazy_ptr's.

llvm-svn: 51277
2008-05-19 21:38:18 +00:00
Dale Johannesen 2e1d5e487b Record weak external linkage in a case where we were
missing it. gcc.dg/darwin-weakimport-2.c.
Handle common and weak differently for darwin ppc32.

llvm-svn: 51201
2008-05-16 20:09:25 +00:00
Dale Johannesen ce4396bc92 Add CommonLinkage; currently tentative definitions
are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both.  The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.

llvm-svn: 51118
2008-05-14 20:12:51 +00:00
Dale Johannesen fd967cf3fa Recommitting EH patch; this should answer most of the
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.

llvm-svn: 49064
2008-04-02 00:25:04 +00:00
Dale Johannesen 5e4e051c2a Revert 49006 for the moment.
llvm-svn: 49046
2008-04-01 20:00:57 +00:00
Dale Johannesen 7d02cf3c9c Emit exception handling info for functions which are
not marked nounwind, or for all functions when -enable-eh
is set, provided the target supports Dwarf EH.

llvm-gcc generates nounwind in the right places; other FEs
will need to do so also.  Given such a FE, -enable-eh should
no longer be needed.

llvm-svn: 49006
2008-03-31 23:40:23 +00:00
Evan Cheng ddc58ff92a Smaller function alignment when optimizing for size.
llvm-svn: 48805
2008-03-25 22:29:46 +00:00
Dan Gohman bdc24adaaf A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.

llvm-svn: 48800
2008-03-25 21:45:14 +00:00
Evan Cheng c799065cc3 Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
Bill Wendling c24ea4fb41 Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!

llvm-svn: 47625
2008-02-26 21:11:01 +00:00
Chris Lattner 7b1431785b Handle \n's in value names for more targets. The asm printers
really really really need refactoring :(

llvm-svn: 47171
2008-02-15 19:04:54 +00:00
Dale Johannesen 6ca3ccf519 Rewrite tblgen handling of subtarget features so
it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to.  Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.

llvm-svn: 47143
2008-02-14 23:35:16 +00:00
Dan Gohman 3a4be0fdef Rename MRegisterInfo to TargetRegisterInfo.
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Nate Begeman f3c89be368 Ident mnemonics appropriately
llvm-svn: 46746
2008-02-05 08:49:09 +00:00
Evan Cheng 32e5347eb8 Get rid of the annoying blank lines before labels.
llvm-svn: 46667
2008-02-02 08:39:46 +00:00
Bill Wendling 1a17ef02c8 If there's no instructions being emitted on X86 for a function, emit a
nop. Emit the nop directly for PPC.

llvm-svn: 46398
2008-01-26 09:03:52 +00:00
Bill Wendling 5079483957 If there are no machine instructions emitted for a function, then insert
a "nop" instruction so that we don't have the function's label associated
with something that it's not supposed to be associated with.

llvm-svn: 46394
2008-01-26 06:51:24 +00:00