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3 Commits

Author SHA1 Message Date
Vincent Lejeune df18804e26 R600: Non vector only instruction can be scheduled on trans unit 
llvm-svn: 187514
 2013-07-31 19:31:56 +00:00
Vincent Lejeune f97af796a9 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Tom Stellard 5a6b0d828b R600: Reorganize lit tests and document how they should be organized 
llvm-svn: 179828
 2013-04-19 02:10:53 +00:00