7 Commits

Author	SHA1	Message	Date
Joerg Sonnenberger	1bbfa7f9d7	[SPARC] Add mulscc. ... llvm-svn: 247940	2015-09-17 20:54:26 +00:00
James Y Knight	89ac11de32	[Sparc] Add more instruction aliases. ... These are mostly from the chart in the SparcV8 spec, section "A.3 Synthetic Instructions". Differential Revision: http://reviews.llvm.org/D9834 llvm-svn: 241461	2015-07-06 16:01:07 +00:00
Tim Northover	5896b066e6	TableGen: fix operand counting for aliases ... TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969	2014-05-16 09:42:04 +00:00
Venkatraman Govindaraju	2a9c430677	[Sparc] Add missing ALU instruction patterns. ... llvm-svn: 202597	2014-03-01 17:51:00 +00:00
Venkatraman Govindaraju	f7eecf80c4	[Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code. ... llvm-svn: 202563	2014-03-01 01:04:26 +00:00
Venkatraman Govindaraju	de98fae368	[Sparc] Add support for parsing synthetic instruction 'mov'. ... llvm-svn: 200965	2014-02-07 09:06:52 +00:00
Venkatraman Govindaraju	5f1cce50e6	[Sparc] Add initial implementation of MC Code emitter for sparc. ... llvm-svn: 198533	2014-01-05 02:13:48 +00:00