499d5f333f
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
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llvm-svn: 67669
2009-03-25 01:48:21 +00:00
5e5a63cf8f
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
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llvm-svn: 67668
2009-03-25 01:47:28 +00:00
9966403e90
Don't print global names twice with -asm-verbose.
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llvm-svn: 67667
2009-03-25 01:08:42 +00:00
7f570d5491
Revert r67655 and r67656, as they are breaking the build. I'm
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not going to persue this further at this time.
llvm-svn: 67666
2009-03-25 00:52:11 +00:00
c3b2111d97
Fix PR3874 by restoring a condition I removed, but making it more
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precise than it used to be.
llvm-svn: 67662
2009-03-25 00:28:58 +00:00
a6e85a19c6
Do not ignore DW_TAG_class_type!
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llvm-svn: 67661
2009-03-25 00:28:40 +00:00
1e7602a20e
LLVM's master Makefile.common is in LLVM_SRC_ROOT, not LLVM_OBJ_ROOT.
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llvm-svn: 67658
2009-03-25 00:09:05 +00:00
9e94538005
oops, I intended to remove this, not comment it out. Thanks Duncan!
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llvm-svn: 67657
2009-03-24 23:48:25 +00:00
9d4d283024
Regenerate configure.
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llvm-svn: 67656
2009-03-24 23:47:11 +00:00
34be8be297
Fix paths; AutoRegen.sh changes its current working directory to be the
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autoconf directory, but these paths need to be relative to the main
source directory.
llvm-svn: 67655
2009-03-24 23:46:25 +00:00
afcd6a3133
Update for autoconf 2.6x;
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llvm-svn: 67654
2009-03-24 23:45:13 +00:00
d1d2c50ea7
Converted a1.ll to unittests.
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llvm-svn: 67652
2009-03-24 21:36:09 +00:00
61837e6dc8
Mention explicitly that the Ada front-end will not bootstrap.
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The configure line had --disable-bootstrap, but it was not
clear that this is essential.
llvm-svn: 67651
2009-03-24 21:16:39 +00:00
f413a88839
Fix PR3845: Avoid stale MachineInstruction pointer reference.
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llvm-svn: 67649
2009-03-24 20:33:17 +00:00
24e02b1043
Fix bash-isms.
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llvm-svn: 67647
2009-03-24 20:21:37 +00:00
e7e5becdd2
simplify logic and get rid of the assumption that operand 0 is the callee
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llvm-svn: 67642
2009-03-24 19:28:39 +00:00
306813cbbb
canonicalize inttoptr and ptrtoint instructions which cast pointers
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to/from integer types that are not intptr_t to convert to intptr_t
then do an integer conversion to the dest type. This exposes the
cast to the optimizer.
llvm-svn: 67638
2009-03-24 18:35:40 +00:00
4d7e4ee799
fix one more fp80 case (used only by Interpreter)
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and streamline code here a bit.
llvm-svn: 67636
2009-03-24 18:16:17 +00:00
d9eb41177a
two changes:
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1. Make instcombine always canonicalize trunc x to i1 into an icmp(x&1). This
exposes the AND to other instcombine xforms and is more of what the code
generator expects.
2. Rewrite the remaining trunc pattern match to use 'match', which
simplifies it a lot.
llvm-svn: 67635
2009-03-24 18:15:30 +00:00
f259f3f312
Change JIT for different layout of fp80.
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llvm-svn: 67629
2009-03-24 17:35:45 +00:00
9fc30d5c30
Add a testcase for the scheduling heuristic introduced in r67586.
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llvm-svn: 67622
2009-03-24 16:38:27 +00:00
c35847e109
more tidying: name the components of PhysReg in the case when
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the target constraint specifies a specific physreg.
llvm-svn: 67618
2009-03-24 15:27:37 +00:00
42eceb3491
Tidy a bit more.
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llvm-svn: 67617
2009-03-24 15:25:07 +00:00
246eda43bd
simplify this code a bit now that "allocation to a vreg class" can never
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fail.
llvm-svn: 67616
2009-03-24 15:22:11 +00:00
efd2d44aa5
I was convinced that it's ok to allow a second i8 return value
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to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.
llvm-svn: 67588
2009-03-24 01:04:34 +00:00
f3746cbc56
Minor compile-time optimization; don't bother checking
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canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.
llvm-svn: 67587
2009-03-24 00:50:07 +00:00
9a658d72db
Add a pre-pass to the burr-list scheduler which makes adjustments to
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help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.
llvm-svn: 67586
2009-03-24 00:49:12 +00:00
a774a99245
Do not emit comments unless -asm-verbose.
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llvm-svn: 67580
2009-03-24 00:17:40 +00:00
32dfb35281
Use a SmallPtrSet instead of std::set.
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llvm-svn: 67578
2009-03-23 23:39:20 +00:00
7fe1b0f50f
Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.
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e.g. allocating for GR32, bh is not used, updating bl spill weight.
bl should get the same spill weight otherwise it will be choosen
as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.
llvm-svn: 67574
2009-03-23 22:57:19 +00:00
c8e54db801
Add sanity check in Clang TableGen backend to check if 'Component' is a string.
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llvm-svn: 67565
2009-03-23 21:54:33 +00:00
93eefa0043
Fix internal representation of fp80 to be the
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same as a normal i80 {low64, high16} rather
than its own {high64, low16}. A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.
llvm-svn: 67562
2009-03-23 21:16:53 +00:00
2441a7df96
README.txt: test commit w/blank line appended
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llvm-svn: 67560
2009-03-23 21:00:45 +00:00
ed0e8d44ce
When unfolding a load during scheduling, the new operator node has
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a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.
And add a few comments.
llvm-svn: 67554
2009-03-23 20:20:43 +00:00
4dc0c6697f
Update test for pr3864.
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llvm-svn: 67545
2009-03-23 18:27:36 +00:00
f858466018
Fix PR3391 and PR3864. Reg allocator infinite looping.
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llvm-svn: 67544
2009-03-23 18:24:37 +00:00
f477262e69
Don't set SUnit::hasPhysRegDefs to true unless the defs are
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actually have uses, which reflects the way it's used.
llvm-svn: 67540
2009-03-23 17:39:36 +00:00
a366da1bf7
Fix canClobberPhysRegDefs to check all SDNodes grouped together
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in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.
llvm-svn: 67531
2009-03-23 16:23:01 +00:00
52c278e54d
Add a new bit to SUnit to record whether a node has implicit physreg
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defs, regardless of whether they are actually used.
llvm-svn: 67528
2009-03-23 16:10:52 +00:00
4f2fea1a21
Now that errs() is properly non-buffered, there's no need to
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explicitly flush it.
llvm-svn: 67526
2009-03-23 15:57:19 +00:00
7135a9d166
Clarify a comment.
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llvm-svn: 67525
2009-03-23 15:54:02 +00:00
21ff35195e
LoopVR is not CFGOnly.
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llvm-svn: 67524
2009-03-23 15:50:52 +00:00
5aabc424b1
Enhance LiveValues to work on PHI operands.
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llvm-svn: 67523
2009-03-23 15:49:37 +00:00
87cd443ae9
Make getOperandNumForIncomingValue and getOperandNumForIncomingBlock
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static member functions, and add getIncomingValueNumForOperand
and getIncomingBlockNumForOperand, which are the respective
inverses.
llvm-svn: 67522
2009-03-23 15:48:29 +00:00
4a683478d5
Correct some comments. Operand numbers start at 0.
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llvm-svn: 67518
2009-03-23 15:40:10 +00:00
968c3b0d6e
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
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llvm-svn: 67512
2009-03-23 08:01:15 +00:00
47c9750f04
Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
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%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.
llvm-svn: 67511
2009-03-23 07:19:58 +00:00
f2b60658ef
fix a bug Alexei Svitkine pointed out.
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llvm-svn: 67510
2009-03-23 06:46:20 +00:00
fb95472123
When we restore signal handlers, restore them back to what they
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were when we came around, not to their default handler. This
should fix PR3848
llvm-svn: 67509
2009-03-23 05:55:36 +00:00
f299a68ee0
factorize signal registration, part of PR3848.
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llvm-svn: 67508
2009-03-23 05:42:29 +00:00
Evan Cheng