55 Commits

Author	SHA1	Message	Date
Amaury de la Vieuville	718ce62b3c	Add support for poly16 vtst and vtstq ... vtst and vtstq currently support poly8 types, but they should also work on poly16. llvm-svn: 190925	2013-09-18 08:33:53 +00:00
Jiangning Liu	1bda93a252	Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions, ... SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL llvm-svn: 190289	2013-09-09 02:21:08 +00:00
Hao Liu	b1852eed38	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions: ... sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshr$ and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu llvm-svn: 189926	2013-09-04 09:29:13 +00:00
Hao Liu	4efa1402fe	Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions ... llvm-svn: 188452	2013-08-15 08:26:30 +00:00
Tim Northover	2fe823a6c3	AArch64: initial NEON support ... Patch by Ana Pazos - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187568	2013-08-01 09:23:19 +00:00