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5 Commits

Author SHA1 Message Date
Craig Topper 5c913e84df [AVX512] Use VMOVAPSZ128rr/VMOVAPS256rr for VR128X/VR256X physreg moves when VLX is supported. 
Ideally we would use VEX encoded moves instead of EVEX if the high 16 registers aren't referenced, but this a good first step.

llvm-svn: 275763
 2016-07-18 06:14:34 +00:00
Craig Topper 298b6d7493 [X86] Re-generate tests using update_llc_test_checks.py to prepare for a future commit. NFC 
llvm-svn: 268883
 2016-05-08 21:33:47 +00:00
Craig Topper 092794b82a Remove Windows line endings in some tests to prepare for a future commit. NFC 
llvm-svn: 268882
 2016-05-08 21:33:44 +00:00
Craig Topper 3bb3f73be3 [X86] Change FeatureIFMA string to 'avx512ifma'. Matches gcc and fixes PR26461. 
llvm-svn: 260069
 2016-02-08 01:23:15 +00:00
Asaf Badouh 655822ab7e [X86][IFMA] adding intrinsics and encoding for multiply and add of unsigned 52bit integer 
VPMADD52LUQ - Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators
 VPMADD52HUQ - Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators

Differential Revision: http://reviews.llvm.org/D16407

llvm-svn: 258680
 2016-01-25 11:14:24 +00:00