c3a6357ee3
Add support for 64-bit logical NOR.
...
llvm-svn: 141029
2011-10-03 21:23:18 +00:00
48a72ca0cb
Add support for 64-bit count leading ones and zeros instructions.
...
llvm-svn: 141028
2011-10-03 21:16:50 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
a279d9bd6a
Add support for 64-bit integer multiply instructions.
...
llvm-svn: 141017
2011-10-03 20:01:11 +00:00
1fef284cf9
Remove unnecessary checking of register operands.
...
llvm-svn: 140872
2011-09-30 19:18:24 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
b381129095
Check values of immediate operands.
...
llvm-svn: 140860
2011-09-30 17:19:21 +00:00
61e256aa69
Mips64 shift instructions.
...
llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
...
immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
...
slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
...
llvm-svn: 140806
2011-09-29 20:37:56 +00:00
c064f2c33e
Convert more tests over to the new atomic instructions.
...
llvm-svn: 140559
2011-09-26 20:27:49 +00:00
4ce4a61cac
Remove +.
...
llvm-svn: 140266
2011-09-21 17:43:48 +00:00
24b6588743
Re-enable some of the disabled tests. Use FileCheck instead of grep to check
...
output.
llvm-svn: 140263
2011-09-21 17:36:30 +00:00
73b5d6ddc1
Delete test cases that generate code for allegrex/psp and cannot be repurposed.
...
llvm-svn: 139652
2011-09-13 22:29:13 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
...
tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
f58d6812a9
Disable tests which generate code for allegrex or psp.
...
llvm-svn: 139632
2011-09-13 20:00:35 +00:00
5624707684
Fix test cases.
...
Generate code for Mips32r1 unless a Mips32r2 feature is tested.
llvm-svn: 139433
2011-09-09 23:14:58 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
...
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
d22a1c6c95
Drop support for Allegrex. Allegrex implements a variant of Mips2.
...
llvm-svn: 139383
2011-09-09 19:00:51 +00:00
df1df7edf1
Change default target architecture from Mips1 to Mips32r1 in preparation for
...
removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
llvm-svn: 139344
2011-09-09 01:13:27 +00:00
474c455060
Disable these tests harder. They're XFAIL'd, but that means they still run, and
...
these tests all infinitely recurse, bringing my system down into swapping hell.
llvm-svn: 139192
2011-09-06 22:08:18 +00:00
912668d998
Better fix for this testcase. Update it to the new EH scheme entirely.
...
llvm-svn: 139039
2011-09-02 21:27:08 +00:00
17706bcffb
Update for new EH stuff. (I'm not sure if this is 100% correct.)
...
llvm-svn: 139038
2011-09-02 21:24:17 +00:00
3767be9aee
Revert r131152, r129796, r129761. This code is currently considered
...
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.
llvm-svn: 138977
2011-09-01 23:07:08 +00:00
fb4161ae88
Use subword loads instead of a 4-byte load when the size of a structure (or a
...
piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
7d7bec5acf
Add test case for r137711.
...
llvm-svn: 137725
2011-08-16 17:32:01 +00:00
2263c10946
Fix handling of double precision loads and stores when Mips1 is targeted.
...
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
2f6b944f56
Test case for 137484
...
llvm-svn: 137486
2011-08-12 18:12:06 +00:00
79d60d0e94
Enclose directive .cprestore with .set macro and nomacro to silence assembler
...
warning.
llvm-svn: 137378
2011-08-11 22:42:31 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
...
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
f3b29992d5
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
...
ANDi, when the instruction does not have any immediate operands.
llvm-svn: 135520
2011-07-19 20:34:00 +00:00
e450358a21
Remove redundant instructions.
...
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
instruction being expanded, instead of masking it in thisMBB.
- Remove redundant Or in EmitAtomicCmpSwap.
llvm-svn: 135495
2011-07-19 18:14:26 +00:00
338879a7f4
Do not treat atomic.load.sub differently than other atomic binary intrinsics.
...
llvm-svn: 135418
2011-07-18 19:58:59 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
...
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
35792089e7
Change the chain input of nodes that load the address of a function. This change
...
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.
llvm-svn: 133811
2011-06-24 19:01:25 +00:00
ca88b4abec
Prevent generation of redundant addiu instructions that compute address of
...
static variables or functions.
llvm-svn: 133803
2011-06-24 17:55:19 +00:00
4c406e7457
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
...
llvm-svn: 133494
2011-06-21 00:40:49 +00:00
5756c16cdf
make the asmparser reject function and type redefinitions. 'Merging' hasn't been
...
needed since llvm-gcc 3.4 days.
llvm-svn: 133248
2011-06-17 07:06:44 +00:00
b90ed2233c
manually upgrade a bunch of tests to modern syntax, and remove some that
...
are either unreduced or only test old syntax.
llvm-svn: 133228
2011-06-17 03:14:27 +00:00
f15601f19a
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
...
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
0683a7212e
Initial support for inline asm memory operand constraints.
...
llvm-svn: 132768
2011-06-09 03:31:05 +00:00
4e9af454f7
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
...
dynamically allocated stack area was not set.
llvm-svn: 132758
2011-06-08 21:28:09 +00:00
08b7a779ef
Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:
...
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
callee-saved register is emitted even when no callee-saved registers are
saved.
- When a callee-saved double precision register is saved, two cfi_offset
directives, one for each of the paired single precision registers, should be
emitted.
llvm-svn: 132703
2011-06-07 02:17:21 +00:00
2446869410
Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
...
llvm-svn: 132448
2011-06-02 01:03:14 +00:00
d84c76f2a7
Test case for r132444.
...
llvm-svn: 132445
2011-06-02 00:25:53 +00:00
98fc4c8bbc
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
...
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
llvm-svn: 132323
2011-05-31 02:54:07 +00:00
bf3c1251e0
This patch implements the thread local storage. Implemented are General
...
Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
llvm-svn: 132322
2011-05-31 02:53:58 +00:00
dd6fcc4e46
Fix PR10046 by updating LiveVariables kill info when splitting live ranges.
...
This only affects targets like Mips where branch instructions may kill virtual
registers. Most other targets branch on flag values, so virtual registers are
not involved.
The problem is that MachineBasicBlock::updateTerminator deletes branches and
inserts new ones while LiveVariables keeps a list of pointers to instructions
that kill virtual registers. That list wasn't properly updated in
MBB::SplitCriticalEdge.
llvm-svn: 132298
2011-05-29 20:10:28 +00:00
b406843fe5
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
...
Need this to prevent emitting illegal conditional move instructions.
llvm-svn: 132240
2011-05-28 01:07:07 +00:00
aa560006ed
Add support for C++ exception handling.
...
llvm-svn: 132131
2011-05-26 18:59:03 +00:00
fa63d3096d
Define WeakRefDirective.
...
llvm-svn: 132098
2011-05-25 23:30:30 +00:00
44eba3ac49
Custom-lower FCOPYSIGN nodes.
...
llvm-svn: 132074
2011-05-25 19:32:07 +00:00
aac670c1c8
Fix lowering of DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 132030
2011-05-25 02:20:00 +00:00
2486729839
Test case for r132003.
...
llvm-svn: 132005
2011-05-24 21:28:18 +00:00
ce4037ebcf
Fix test case.
...
llvm-svn: 131988
2011-05-24 19:37:15 +00:00
0f30561bae
Revision 131986 test case.
...
llvm-svn: 131987
2011-05-24 19:29:37 +00:00
6af5bd2537
Add pattern for double-to-integer conversion. Patch by Sasa Stankovic.
...
llvm-svn: 131927
2011-05-23 22:16:43 +00:00
f9e5750fc8
Change StackDirection from StackGrowsUp to StackGrowsDown.
...
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
the stack pointer) are set before instruction selection is completed. There is
no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
no longer necessary to assign negative offsets to fixed objects for incoming
arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in
MipsFrameLowering::adjustMipsStackFrame.
llvm-svn: 131915
2011-05-23 20:16:59 +00:00
43407fe633
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
...
saving and restoring them.
llvm-svn: 131745
2011-05-20 18:39:33 +00:00
fe4f9d5977
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
...
llvm-svn: 131714
2011-05-20 02:30:51 +00:00
9e6a8cca5d
Align i64 arguments to 64 bit boundaries.
...
llvm-svn: 131668
2011-05-19 20:29:48 +00:00
3bace5d223
Remove LLVM IR metadata in test case committed in r130847.
...
llvm-svn: 130849
2011-05-04 18:28:36 +00:00
23e8ecf125
Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp.
...
llvm-svn: 130847
2011-05-04 17:54:27 +00:00
5b5abb4ea1
Don't run this test through -regalloc=basic.
...
The basic allocator is really bad about hinting, so it doesn't eliminate all
copies when physreg joining is disabled.
llvm-svn: 130817
2011-05-04 01:01:44 +00:00
0e7ee666b7
Lower BlockAddress node when relocation-model is static.
...
llvm-svn: 130131
2011-04-25 17:10:45 +00:00
bf78618db6
Make tests register allocation independent again.
...
llvm-svn: 129739
2011-04-19 00:14:43 +00:00
2cb3aa30dd
Re-enable test o32_cc_vararg.ll.
...
llvm-svn: 129616
2011-04-15 22:23:09 +00:00
279169771b
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
...
llvm-svn: 129594
2011-04-15 19:52:08 +00:00
b53a00d2cb
Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
...
Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.
Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
llvm-svn: 129421
2011-04-13 00:38:32 +00:00
d6f1c58914
Fix handling of functions with internal linkage.
...
llvm-svn: 129099
2011-04-07 19:51:44 +00:00
1ec41e2bd9
These tests no longer require linear scan because reserved register coalescing is now universal.
...
llvm-svn: 128936
2011-04-05 21:40:41 +00:00
93f898f643
Add code for analyzing FP branches. Clean up branch Analysis functions.
...
llvm-svn: 128718
2011-04-01 17:39:08 +00:00
f4c9754d5c
Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
...
Add an extra run with -regalloc=basic to keep them honest.
llvm-svn: 128654
2011-03-31 18:42:43 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
...
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
66559ba79a
Revert "Re-enable test and hope to silence the buildbots", still broken.
...
llvm-svn: 127369
2011-03-09 22:48:46 +00:00
6492ef1237
Add a testcase for the addc improvements introduced some commits ago. Patch by Akira Hatanaka
...
llvm-svn: 127358
2011-03-09 21:05:32 +00:00
961908982f
Re-enable test and hope to silence the buildbots
...
llvm-svn: 127357
2011-03-09 21:00:16 +00:00
bd2f81c87b
try to make o32 cc tests less specific to silence some buildbots. The test isn't enabled yet, this is will be done in a subsequent commit. Patch by Akira Hatanaka.
...
llvm-svn: 127356
2011-03-09 20:59:05 +00:00
048ffabe78
Improve varags handling, with testcases. Patch by Sasa Stankovic
...
llvm-svn: 127349
2011-03-09 19:22:22 +00:00
434248a62c
Improve div/rem node handling on mips. Patch by Akira Hatanaka
...
llvm-svn: 127034
2011-03-04 21:03:24 +00:00
d631599e38
Add testcase for r127032
...
llvm-svn: 127033
2011-03-04 20:48:39 +00:00
62f759791a
Be nice to Xcore and the XMOS assembler and avoid quoting section names
...
that contain only letters, digits and the characters "_" and ".".
llvm-svn: 127028
2011-03-04 20:03:14 +00:00
f8198e4311
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
...
llvm-svn: 127027
2011-03-04 20:01:52 +00:00
852ab890b5
Bug#9033: For the ELF assembler output, always quote the section name.
...
llvm-svn: 126963
2011-03-03 22:31:08 +00:00
4be2ab4894
Disable this test for now...
...
llvm-svn: 125361
2011-02-11 02:59:08 +00:00
6e4b229c02
Add mips o32 tests again with the hope that the buildbot won't complaint again
...
llvm-svn: 125316
2011-02-10 23:37:20 +00:00
788afe6d3a
Remove the test to silence the buildbot, will check it in again with a proper fix soon
...
llvm-svn: 125305
2011-02-10 20:10:17 +00:00
61a61e9da3
Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka with some small modifications by me.
...
llvm-svn: 125292
2011-02-10 18:05:10 +00:00
4dc73fa075
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka
...
llvm-svn: 123760
2011-01-18 19:29:17 +00:00
ec517cdf24
Update tests.
...
llvm-svn: 123591
2011-01-16 18:02:57 +00:00
d47180e45e
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
...
llvm-svn: 121377
2010-12-09 17:32:30 +00:00
f0c6e3780d
Match a pattern generated by a dag combiner opt where:
...
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))
Thanks to Akira for pointing that.
llvm-svn: 121163
2010-12-07 19:00:20 +00:00
c24048a718
If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.
...
llvm-svn: 121059
2010-12-06 22:39:26 +00:00
03c0330176
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
...
llvm-svn: 118864
2010-11-12 00:38:32 +00:00
a4ceea8cd8
Add a test to the previous added clo instruction. Patch by Akira again
...
llvm-svn: 118668
2010-11-10 02:22:44 +00:00
f3e9a48584
Enable machine sinking critical edge splitting. e.g.
...
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
llvm-svn: 114372
2010-09-20 22:52:00 +00:00
68c30907cc
Correct bogus module triple specifications.
...
llvm-svn: 112469
2010-08-30 10:48:29 +00:00
160695fecb
Fix PR7174, a couple o Mips fixes:
...
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.
Patch by stetorvs@gmail.com
llvm-svn: 108820
2010-07-20 08:37:04 +00:00
ea7863647b
Fix Mips PR7473. Patch by stetorvs@gmail.com
...
llvm-svn: 108816
2010-07-20 07:58:51 +00:00
4fee6f3bdd
Start function numbering at 0.
...
llvm-svn: 101638
2010-04-17 16:29:15 +00:00
f118f9788b
Split big test into multiple directories to cater to
...
those who don't build all targets.
llvm-svn: 100688
2010-04-07 20:43:35 +00:00
fb4193625a
Delete useless trailing semicolons.
...
llvm-svn: 92740
2010-01-05 17:55:26 +00:00
2db07581b7
Support PIC loading of constant pool entries
...
llvm-svn: 89863
2009-11-25 12:17:58 +00:00
0b2099ad5f
Unbreak test, Bruno please check.
...
llvm-svn: 89329
2009-11-19 07:18:49 +00:00
4713b282ce
- Add sugregister logic to handle f64=(f32,f32).
...
- Support mips1 like load/store of doubles:
Instead of:
sdc $f0, X($3)
Generate:
swc $f0, X($3)
swc $f1, X+4($3)
llvm-svn: 89322
2009-11-19 06:06:13 +00:00
8ca5d4b9ad
xfail for now. It has been failing.
...
llvm-svn: 88892
2009-11-16 05:44:04 +00:00
537e409c58
- Fix a small bug while handling target constant pools (one param was missing).
...
- Add a smarter constant pool loading, instead of:
lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)
Generate:
lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)
llvm-svn: 88886
2009-11-16 04:33:42 +00:00
c8054d90fb
Eliminate more uses of llvm-as and llvm-dis.
...
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
0d4bbf2c4a
Remove obsolete -f flags.
...
llvm-svn: 79992
2009-08-25 15:38:29 +00:00
68535f7603
reintroduce support for Mips "small" section handling. This is
...
implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.
llvm-svn: 78900
2009-08-13 06:28:06 +00:00
0f16ea5c30
Pass target triple string in to TargetMachine constructor.
...
This is not just a matter of passing in the target triple from the module;
currently backends are making decisions based on the build and host
architecture. The goal is to migrate to making these decisions based off of the
triple (in conjunction with the feature string). Thus most clients pass in the
target triple, or the host triple if that is empty.
This has one important change in the way behavior of the JIT and llc.
For the JIT, it was previously selecting the Target based on the host
(naturally), but it was setting the target machine features based on the triple
from the module. Now it is setting the target machine features based on the
triple of the host.
For LLC, -march was previously only used to select the target, the target
machine features were initialized from the module's triple (which may have been
empty). Now the target triple is taken from the module, or the host's triple is
used if that is empty. Then the triple is adjusted to match -march.
The take away is that -march for llc is now used in conjunction with the host
triple to initialize the subtarget. If users want more deterministic behavior
from llc, they should use -mtriple, or set the triple in the input module.
llvm-svn: 77946
2009-08-03 04:03:51 +00:00
26aff56462
Remove SectionKind::Small*. This was only used on mips, and is apparently
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a sad mistake that is regretted. :)
llvm-svn: 76935
2009-07-24 03:11:51 +00:00
0cf7f5d6d2
Revert commit 76707, it was breaking the llvm-gcc build
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on linux platforms. The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html
llvm-svn: 76733
2009-07-22 10:35:05 +00:00
8ebaec6b27
set the ELF "small" flag on objects that end up in .rodata.cst4 consistently,
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updating a mips testcase to expect it.
llvm-svn: 76707
2009-07-22 00:41:56 +00:00
a5b9645c4b
Split the Add, Sub, and Mul instruction opcodes into separate
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integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
llvm-svn: 72897
2009-06-04 22:49:04 +00:00
0a9ea80013
This looks like it passes now.
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llvm-svn: 72485
2009-05-27 17:43:21 +00:00
6de96a1b5d
Add the private linkage.
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llvm-svn: 62279
2009-01-15 20:18:42 +00:00
1407484178
The list-td and list-tdrr schedulers don't yet support physreg
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scheduling dependencies. Add assertion checks to help catch
this.
It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.
llvm-svn: 62177
2009-01-13 20:24:13 +00:00
ddacbb39ab
Fix PR2667: add soft float support for sint_to_fp/uint_to_fp
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where the argument is an apint, or smaller than the minimum
size for which there is a libcall (i32).
llvm-svn: 58994
2008-11-10 17:36:26 +00:00
8475d56794
Turn on LegalizeTypes, the new type legalization
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codegen infrastructure, by default. Please report
any breakage to the mailing lists.
llvm-svn: 58232
2008-10-27 08:42:46 +00:00
da9b752883
FIX PR2794. Make sure SIGN_EXTEND_INREG nodes introduced by LegalizeSetCCOperands are leglized. Patch by Richard Pennington.
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llvm-svn: 57460
2008-10-13 18:46:18 +00:00
595229a15a
Added testcase for bswap allegrexel intrinsic
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llvm-svn: 56225
2008-09-15 19:38:11 +00:00
93da7e6924
Support added for ctlz intrinsic, test case added.
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llvm-svn: 54516
2008-08-08 06:16:31 +00:00
6067b44985
[Last] Batch 7 of Mips CodeGen tests
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llvm-svn: 54512
2008-08-08 04:12:42 +00:00
b60eebbab8
Batch 6 of Mips CodeGen tests
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llvm-svn: 54511
2008-08-08 04:11:30 +00:00
9c8b9d4606
Batch 5 of Mips CodeGen tests
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llvm-svn: 54510
2008-08-08 04:09:57 +00:00
32d4b5a44e
Batch 4 of Mips CodeGen tests
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llvm-svn: 54509
2008-08-08 04:08:30 +00:00
118a9e4813
Batch 3 of Mips CodeGen tests
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llvm-svn: 54508
2008-08-08 04:05:51 +00:00
6b9077a5e4
Batch 2 of Mips CodeGen tests
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llvm-svn: 54507
2008-08-08 04:03:25 +00:00
98ab9b334b
Batch 1 of Mips CodeGen tests, more coming...
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I had a lot of simple local codegen tests and they are now ready to be placed
in test/CodeGen.
llvm-svn: 54506
2008-08-08 03:58:34 +00:00
Akira Hatanaka