cac328f25e
[X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.
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llvm-svn: 294132
2017-02-05 18:33:31 +00:00
6b4499a393
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output.
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llvm-svn: 227963
2015-02-03 11:03:57 +00:00
a422b09ae3
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
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llvm-svn: 192567
2013-10-14 04:55:01 +00:00
7158745e55
Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
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llvm-svn: 192565
2013-10-14 01:21:22 +00:00
5fb5bd3373
Allow non-AVX form of pmovmskb to take a GR64 operand.
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llvm-svn: 192341
2013-10-10 05:33:31 +00:00
8eb45a4ef6
Add the remaining Intel SHA instructions
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Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.
llvm-svn: 190754
2013-09-14 15:03:21 +00:00
1650175de6
Partial support for Intel SHA Extensions (sha1rnds4)
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Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.
Support for the remaining instructions will follow in a separate patch.
llvm-svn: 190611
2013-09-12 15:51:31 +00:00
375249a417
Add encoding tests for flds/filds
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llvm-svn: 129589
2011-04-15 19:25:31 +00:00
889a508157
Recognize leavel and leaveq aliases for leave.
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Validate encoding of leave in 64bit mode.
llvm-svn: 125795
2011-02-17 23:36:39 +00:00
2406b7d179
Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.
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These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.
llvm-svn: 125446
2011-02-12 23:24:13 +00:00
4ca7bb52d0
move X86 subdir up a level
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llvm-svn: 115292
2010-10-01 04:32:20 +00:00
Craig Topper