3ebf848b47
llvm-mc/X86: Sketch match functions for immediates and memory operands.
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Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.
llvm-svn: 77728
2009-07-31 20:53:16 +00:00
ca9a4f1045
PR4662: Fix a crash introduced by the recent LLVMContext changes.
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llvm-svn: 77716
2009-07-31 19:36:47 +00:00
4d2c0f9008
switch off of 'Section' onto MCSection. We're not properly using
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MCSection subclasses yet, but this is a step in the right direction.
llvm-svn: 77708
2009-07-31 18:48:30 +00:00
be8422e8e0
Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
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to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.
llvm-svn: 77705
2009-07-31 18:35:56 +00:00
fc0264a38e
fix PR4650: we only track sizes for certain objects, so only put something
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into the mergable section if it is one of our special cases. This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.
llvm-svn: 77679
2009-07-31 16:17:13 +00:00
a93183b8c9
Add this test back, the check pattern was too strict.
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llvm-svn: 77662
2009-07-31 03:11:49 +00:00
8f416a5138
Remove this test while I figure out why it is failing.
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llvm-svn: 77659
2009-07-31 02:46:36 +00:00
b6d6aa2d22
llvm-mc: Match a few X86 instructions.
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- This is "experimental" code, I am feeling my way around and working out the
best way to do things (and learning tblgen in the process). Comments welcome,
but keep in mind this stuff will change radically.
- This is enough to match "subb" and friends, but not much else. The next step is to
automatically generate the matchers for individual operands.
llvm-svn: 77657
2009-07-31 02:32:59 +00:00
5811ab5cf3
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
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llvm-svn: 77642
2009-07-30 23:29:25 +00:00
16e5124a82
Do not use abbrev while writing NamedMDNode name.
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llvm-svn: 77637
2009-07-30 23:06:35 +00:00
0bfc8312c2
Darwin assembler now recognizes "orn", so remove workaround.
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llvm-svn: 77627
2009-07-30 21:51:41 +00:00
ce774e2383
Darwin assembler now supports "rrx", so remove workaround.
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llvm-svn: 77625
2009-07-30 21:38:40 +00:00
79c079b478
Cleanup and include code selection for some frame index cases.
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llvm-svn: 77622
2009-07-30 18:56:48 +00:00
e62288fdd4
Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch.
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When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.
This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.
Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.
llvm-svn: 77582
2009-07-30 08:33:02 +00:00
49a6f16b7c
Add a new register class to describe operands that can't be SP,
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due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.
llvm-svn: 77565
2009-07-30 01:56:29 +00:00
e3493a91cc
tbb / tbh instructions only branch forward, not backwards.
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llvm-svn: 77522
2009-07-29 23:20:20 +00:00
1f58eed638
Add VFP3 D registers to the DPR register class.
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llvm-svn: 77521
2009-07-29 23:03:41 +00:00
27c87fff7f
Read and write NamedMDNode.
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llvm-svn: 77517
2009-07-29 22:34:41 +00:00
98ddd164d8
Fix PR4645 which was fallout from the fix for PR4641.
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- Call RAUW to delete all instructions (this is a patch from Nick Lewycky).
llvm-svn: 77512
2009-07-29 22:00:43 +00:00
56c89e70fe
xfail for now.
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llvm-svn: 77478
2009-07-29 17:40:28 +00:00
cf19885a32
Change Neon VLDn intrinsics to return multiple values instead of really
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wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
llvm-svn: 77468
2009-07-29 16:39:22 +00:00
013c8e5474
Just discard the output, no need to turn it back into text.
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llvm-svn: 77439
2009-07-29 06:14:52 +00:00
1d3defa392
don't dump .bc file to stdout, and simplify this to a trivial testcase.
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llvm-svn: 77436
2009-07-29 05:32:07 +00:00
c5397abb52
fix PR4584 with a trivial patch now that the pieces are in place.
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llvm-svn: 77434
2009-07-29 05:20:33 +00:00
f82326b984
Bulk erasing instructions without RAUWing them is unsafe. Instead, break them
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into a new BB that has no predecessors.
llvm-svn: 77433
2009-07-29 05:17:50 +00:00
c6d70ae063
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
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llvm-svn: 77422
2009-07-29 02:18:14 +00:00
dce1e4949e
Add a couple more tests for the ptest intrinsics to make sure we're
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grabbing them all correctly.
llvm-svn: 77413
2009-07-29 00:51:15 +00:00
f7802a33ce
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower
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to ptest instruction plus setcc. Revamp ptest instruction. Add test.
llvm-svn: 77407
2009-07-29 00:28:05 +00:00
2f84b5ab46
Slightly reformat LDA tests to ease grepping.
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llvm-svn: 77398
2009-07-28 23:40:40 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
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llvm-svn: 77364
2009-07-28 20:53:24 +00:00
68bb69d6e3
Remove support for ORN to workaround <rdar://problem/7096522>.
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llvm-svn: 77363
2009-07-28 20:51:25 +00:00
865c6298d7
Add workaround for <rdar://problem/7098328>.
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llvm-svn: 77340
2009-07-28 18:15:38 +00:00
ebbbf451c9
fix testcase for previous patch.
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llvm-svn: 77338
2009-07-28 18:04:18 +00:00
513a36b63d
Fix PR4639, a ELF-TLS regression from some of my refactoring.
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llvm-svn: 77336
2009-07-28 17:57:51 +00:00
e82862e24e
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
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llvm-svn: 77329
2009-07-28 17:06:49 +00:00
12da273f90
tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.
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llvm-svn: 77305
2009-07-28 07:38:35 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
31a9b9880b
Teach instcombine to respect and preserve inbounds. Add inbounds
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to a few tests where it is required for the expected transformation.
llvm-svn: 77290
2009-07-28 01:40:03 +00:00
57b51d9f82
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
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llvm-svn: 77275
2009-07-27 23:34:12 +00:00
eb6bb32bef
llvm-mc: Implement .abort fully in the front end
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llvm-svn: 77272
2009-07-27 23:20:52 +00:00
1639c3905e
Add a new keyword 'inbounds' for use with getelementptr. See the
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LangRef.html changes for details.
llvm-svn: 77259
2009-07-27 21:53:46 +00:00
782f242fd7
Add ".w" suffix for wide thumb-2 instructions.
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llvm-svn: 77199
2009-07-27 16:31:55 +00:00
a77a182b04
Test case to check that separate section is created for a global variable specified with section attribute.
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llvm-svn: 77195
2009-07-27 16:20:41 +00:00
9c7f808201
Change the assembly syntax for nsw, nuw, and exact, putting them
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after their associated opcodes rather than before. This makes them
a little easier to read.
llvm-svn: 77194
2009-07-27 16:11:46 +00:00
57af4ece60
update testcase.
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llvm-svn: 77192
2009-07-27 15:52:58 +00:00
8e58bc9ed4
put normal data into .data instead of .data.rel on elf systems.
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llvm-svn: 77116
2009-07-26 03:06:11 +00:00
397792d981
finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal
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for now. Make the section switching directives more consistent
by not including \n and including \t for them all.
llvm-svn: 77107
2009-07-26 01:24:18 +00:00
5b42b45fb9
simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bit
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and make it more aggressive, we now put:
const int G2 __attribute__((weak)) = 42;
into the text (readonly) segment like gcc, previously we put
it into the data (readwrite) segment.
llvm-svn: 77104
2009-07-26 00:51:36 +00:00
8a37bbebfd
Add support for ARM Neon VREV instructions.
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Patch by Anton Korzh, with some modifications from me.
llvm-svn: 77101
2009-07-26 00:39:34 +00:00
2de9510572
add the most expedient hack to fix PR4619, along with a testcase.
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Thanks to Rafael for the great example.
llvm-svn: 77083
2009-07-25 17:57:37 +00:00
Daniel Dunbar