Commit Graph

345710 Commits

Author SHA1 Message Date
Roman Lebedev 398b497cd0
[NFC] LoopRotate: do issue debug message when not rotating due to instr count
It is somewhat problematic to notice this issue otherwise.
2020-03-17 09:26:09 +03:00
Vitaly Buka 8620bb9534 [lld] Fix "loop variable creates a copy" warning 2020-03-16 22:52:49 -07:00
Jason Molenda 8aa07f81b8 Remove the old SecTaskAccess entry from debugserver's plist
<rdar://problem/60230324>
2020-03-16 21:54:32 -07:00
Stefanos Baziotis 3f3bda1c37 [LoopTerminology] Minor fixes in loop rotation 2020-03-17 06:34:02 +02:00
QingShan Zhang 0b126eec6d [NFC][PowerPC] Simplify the logic in lower select_cc
The logic in select_cc is messy and hard to follow. This is a NFC patch to simplify the logic.

Differential Revision: https://reviews.llvm.org/D75834
2020-03-17 03:47:39 +00:00
Serguei Katkov 80c351cdb6 [InstCombine] Transform to undef incorrect atomic unordered mem intrinsics
According to LangRef:
If len is not a positive integer multiple of element_size, then the behaviour of the intrinsic is undefined.

Add InstCombine rule to transform intrinsic to undef operation.

This is a follow-up for D76116.

Reviewers: reames
Reviewed By: reames
Subscribers: hiraditya, jfb, dantrushin, llvm-commits
Differential Revision: https://reviews.llvm.org/D76215
2020-03-17 10:20:16 +07:00
Chen Zheng fa72b29bec [PowerPC] add test cases for target hook isProfitableToHoist - NFC 2020-03-16 23:07:30 -04:00
Uday Bondhugula 332f0b3cd4 Affine expr simplification for add of const multiple of same expression
- Detect "c_1 * expr + c_2 * expr" as (c_1 + c_2) * expr
- subsumes things like 'expr - expr' and "expr * -1 + expr" as 0.
- change AffineConstantExpr ctor to allow default null init

Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D76233
2020-03-17 08:22:17 +05:30
Vitaly Buka f20dcc31e3 Fix unused function warning 2020-03-16 19:45:36 -07:00
Vitaly Buka f0714cbb6a [sanitizer] Fix warning on windows
Return value is not used anyway as PTHREAD_JOIN is not implemented.
2020-03-16 19:17:03 -07:00
Michael Liao d00d6a19dd Fix `-Wpedantic` warning. NFC. 2020-03-16 22:06:23 -04:00
Shengchen Kan 39bcc76a92 [X86] Disable nop padding before instruction following hardcode
Reviewers: reames, MaskRay, craig.topper, LuoYuanke, jyknight

Reviewed By: LuoYuanke

Subscribers: annita.zhang, llvm-commits, hiraditya

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76176
2020-03-17 09:45:12 +08:00
River Riddle 032743e18f [mlir] Add support for the attribute verifiers in the dialect declaration generator.
Summary: This adds bitfields that map to the dialect attribute verifier hooks. This also moves over the Test dialect to have its declaration generated.

Differential Revision: https://reviews.llvm.org/D76254
2020-03-16 18:32:23 -07:00
Douglas Gliner ac48b1885a [Support] Change isatty to is_displayed
Currently, when building with the Unix support library and `isatty` does
not exist for the target platform (i.e. `HAVE_ISATTY` is false),
compilation of the file `raw_ostream.cpp` will fail due to direct use of
`isatty` in the function `raw_fd_ostream::preferred_buffer_size()`.

Use is_displayed() to fix the problem.

Reviewed By: probinson, MaskRay

Differential Revision: https://reviews.llvm.org/D75278
2020-03-16 18:27:43 -07:00
Craig Topper 85726bbcba [X86] Disable fast-isel call lowering for functions with vXi1 arguments on avx512.
This fails an assert because the type is marked in the calling
convention td file as needing promotion, but the code doesn't know
how to do it.

It also much more complicated because we try to pass these in
xmm/ymm/zmm registers. As of a few weeks ago we do this promotion
from getRegisterTypeForCallingConv before the td file generated
code gets involved.
2020-03-16 18:20:42 -07:00
Adrian Prantl 90a2fbdb04 Switch to TypeSystemClang over to CreateDeserialized() (NFC)
which is the more appropriate API for its use-case.

Differential Revision: https://reviews.llvm.org/D75715
2020-03-16 18:11:36 -07:00
Sriraman Tallam c3f0ceab0f Add target to test basicblock-sections-mir-parse.mir
This test fails on ppc which was unintended.

Revision: D73674.
2020-03-16 18:03:23 -07:00
River Riddle bd5941b9ce [mlir] Remove the PatternState class and simplify PatternMatchResult.
Summary: PatternState was a mechanism to pass state between the match and rewrite calls of a RewritePattern. With the rise of matchAndRewrite, this class is unused and unnecessary. This revision removes PatternState and simplifies PatternMatchResult to just be a LogicalResult. A future revision will replace all usages of PatternMatchResult/matchSuccess/matchFailure with LogicalResult equivalents.

Differential Revision: https://reviews.llvm.org/D76202
2020-03-16 17:55:54 -07:00
Uday Bondhugula d811aee5d9 [MLIR][NFC] update/clean up affine PDT, related utils, its test case
- rename vars that had inst suffixes (due to ops earlier being
  known as insts); other renames for better readability
- drop unnecessary matches in test cases
- iterate without block terminator
- comment/doc updates
- instBodySkew -> affineForOpBodySkew

Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D76214
2020-03-17 06:12:16 +05:30
Eric Christopher 8b3b04eb41 Make isValidImmForSVEVecImmAddrMode inline static rather than just static.
Fixes -Werror builds.
2020-03-16 17:39:01 -07:00
Philip Reames 5f7772004b [Tests] Add test coverage for prefix selection logic
Note that I'm not asserting this code is correct; I'm simply adding coverage for what's there already.  I'm reasonable sure the logic works for existing relaxable instructions, but I wouldn't be suprised if there were incorrect cases for other instructions.  (i.e. is it legal to add prefixes to all instructions?)
2020-03-16 17:27:44 -07:00
Dmitry Mikulin fbb23c9714 Fix profiling options on PS4 target:
- libclang_rt.profile should be added when -fcs-profile-generate is on thecommand line.
- OPT_fno_profile_instr_generate was used as a negative for OPT_fprofile_generate. Fix it to use OPT_fno_profile_generate.

Differential Revision: https://reviews.llvm.org/D75274
2020-03-16 16:52:47 -07:00
Saar Raz 19fccc52ff [Concepts] Fix incorrect control flow when TryAnnotateTypeConstraint annotates an invalid template-id
TryAnnotateTypeConstraint could annotate a template-id which doesn't end up being a type-constraint,
in which case control flow would incorrectly flow into ParseImplicitInt.

Reenter the loop in this case.
Enable relevant tests for C++20. This required disabling typo-correction during TryAnnotateTypeConstraint
and changing a test case which is broken due to a separate bug (will be reported and handled separately).
2020-03-17 01:49:42 +02:00
Evgenii Stepanov 2a3723ef11 [memtag] Plug in stack safety analysis.
Summary:
Run StackSafetyAnalysis at the end of the IR pipeline and annotate
proven safe allocas with !stack-safe metadata. Do not instrument such
allocas in the AArch64StackTagging pass.

Reviewers: pcc, vitalybuka, ostannard

Reviewed By: vitalybuka

Subscribers: merge_guards_bot, kristof.beyls, hiraditya, cfe-commits, gilang, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D73513
2020-03-16 16:35:25 -07:00
LLVM GN Syncbot 78ce190803 [gn build] Port df082ac45a 2020-03-16 23:09:12 +00:00
Sriraman Tallam df082ac45a Basic Block Sections support in LLVM.
This is the second patch in a series of patches to enable basic block
sections support.

This patch adds support for:

* Creating direct jumps at the end of basic blocks that have fall
through instructions.
* New pass, bbsections-prepare, that analyzes placement of basic blocks
in sections.
* Actual placing of a basic block in a unique section with special
handling of exception handling blocks.
* Supports placing a subset of basic blocks in a unique section.
* Support for MIR serialization and deserialization with basic block
sections.

Parent patch : D68063
Differential Revision: https://reviews.llvm.org/D73674
2020-03-16 16:06:54 -07:00
Stefanos Baziotis 30dc342f08 [LoopTerminology] Rotated Loops images 2020-03-17 01:02:19 +02:00
Stefanos Baziotis 7fa204580d [LoopTerminology] Rotated Loops 2020-03-17 00:54:26 +02:00
Artem Belevich 74bf95d71d [CUDA] Updated CompileCudaWithLLVM doc. 2020-03-16 15:49:41 -07:00
Feng Liu 166f83f436 [QuantOps] Add the quant region definition
Summary:
This regional op in the QuantOps dialect will be used to wrap
high-precision ops into atomic units for quantization. All the values
used by the internal ops are captured explicitly by the op inputs. The
quantization parameters of the inputs and outputs are stored in the
attributes.

Subscribers: jfb, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, Joonsoo, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75972
2020-03-16 15:44:43 -07:00
Craig Topper 378b1e6080 [X86] Assign avx512bf16 instructions to the SSEPackedSingle ExeDomain. 2020-03-16 14:07:01 -07:00
Benjamin Kramer 05ff3323e0 [AArch64] Remove unused variable 2020-03-16 21:59:55 +01:00
River Riddle 2d723d4ad5 [mlir] Avoid the use of auto in templates to fix MSVC build
MSVC is unable to deduce template types when the type involves auto.
2020-03-16 13:55:16 -07:00
Siva Chandra Reddy 78d622a48c [libc] Add a README.md file to the AOR directory.
Also, add config.mk file which will help test the implementations in the
"math" directory for x86_64 with a simple "make check".
2020-03-16 12:29:24 -07:00
Nico Weber 623cb95eb3 Revert "[InstSimplify] Simplify calls with "returned" attribute"
This reverts commit 45555c3819.
Causes clang crashes in some causes, see comments on
https://reviews.llvm.org/D75815 for details (including
repro steps).
2020-03-16 15:21:30 -04:00
Kristof Beyls 0928368f62 [libc] Provide Arm Optimized Routines for the LLVM libc project.
This adds the Arm Optimized Routines (see
https://github.com/ARM-software/optimized-routines) source code under the
the LLVM license. The version of the code provided in this patch is v20.02
of the Arm Optimized Routines project.

This entire contribution is being committed as is even though it does
not currently fit the LLVM libc model and does not follow the LLVM
coding style. In the near future, implementations from this patch will be
moved over to their right place in the LLVM-libc tree. This will be done
over many small patches, all of which will go through the normal LLVM code
review process. See this libc-dev post for the plan:
http://lists.llvm.org/pipermail/libc-dev/2020-March/000044.html

Differential revision of the original upload: https://reviews.llvm.org/D75355
2020-03-16 12:19:31 -07:00
River Riddle 9b1513866f [mlir][NFC] Add missing include for std::string. 2020-03-16 12:13:31 -07:00
Francesco Petrogalli 0f2b68d9c7 Implement IR intrinsics for gather prefetch.
Summary:
Intrinsics and relative codegen has been implemented for the following
SVE instructions:

1. PRF<T> <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit          scaled offset
2. PRF<T> <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] -> 32-bit unpacked scaled offset
3. PRF<T> <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]        -> 64-bit          scaled offset
4. PRF<T> <prfop>, <Pg>, [<Zn>.S{, #<imm>}]       -> 32-bit element
5. PRF<T> <prfop>, <Pg>, [<Zn>.D{, #<imm>}]       -> 64-bit element

The instructions are associated the following intrinsics, respectively:

1. void @llvm.aarch64.sve.gather.prf<T>.scaled.<mod>.nx4vi32(
          i8* %base,
          <vscale x 4 x i32> %offset,
          <vscale x 4 x i1> %Pg,
          i32 %prfop)

2. void @llvm.aarch64.sve.gather.prf<T>.scaled.<mod>.nx2vi32(
          i8* %base,
          <vscale x 2 x i32> %offset,
          <vscale x 2 x i1> %Pg,
          i32 %prfop)

3. void @llvm.aarch64.sve.gather.prf<T>.scaled.nx2vi64(
          i8* %base,
          <vscale x 2 x i64> %offset,
          <vscale x 2 x i1> %Pg,
          i32 %prfop)

4. void @llvm.aarch64.sve.gather.prf<T>.nx4vi32(
          <vscale x 4 x i32> %bases,
          i64 %imm,
          <vscale x 4 x i1> %Pg,
          i32 %prfop)

5. void @llvm.aarch64.sve.gather.prf<T>.nx2vi64(
          <vscale x 2 x i64> %bases,
          i64 %imm,
          <vscale x 2 x i1> %Pg,
          i32 %prfop)

The intrinsics are the IR counterpart of the following SVE ACLE functions:

* void svprf<T>(svbool_t pg, const void *base, svprfop op)
* void svprf<T>_vnum(svbool_t pg, const void *base, int64_t vnum, svprfop op)
* void svprf<T>_gather[_u32base](svbool_t pg, svuint32_t bases, svprfop op)
* void svprf<T>_gather[_u64base](svbool_t pg, svuint64_t bases, svprfop op)
* void svprf<T>_gather_[s32]offset(svbool_t pg, const void *base, svint32_t offsets, svprfop op)
* void svprf<T>_gather_[u32]offset(svbool_t pg, const void *base, svint32_t offsets, svprfop op)
* void svprf<T>_gather_[s64]offset(svbool_t pg, const void *base, svint64_t offsets, svprfop op)
* void svprf<T>_gather_[u64]offset(svbool_t pg, const void *base, svint64_t offsets, svprfop op)
* void svprf<T>_gather[_u32base]_offset(svbool_t pg, svuint32_t bases, int64_t offset, svprfop op)
* void svprf<T>_gather[_u64base]_offset(svbool_t pg, svuint64_t bases,int64_t offset, svprfop op)

Reviewers: andwar, sdesmalen, efriedma, rengolin

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75580
2020-03-16 18:52:35 +00:00
Huihui Zhang 0616e9964b [InstSimplify][SVE] Fix SimplifyGEPInst for scalable vector.
Summary:
Skip folds that rely on DataLayout::getTypeAllocSize(). For scalable
vector, only minimal type alloc size is known at compile-time.

Reviewers: sdesmalen, efriedma, spatel, apazos

Reviewed By: efriedma

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75892
2020-03-16 11:46:12 -07:00
Matt Arsenault b0bdb186f5 Utils: Always set alignment when expanding mem intrinsics
This was creating natural aligned loads and stores, which may not be
the case. The target could request a wider type load with less
alignment.
2020-03-16 14:34:29 -04:00
Matt Arsenault 05e7d8d6ce TTI: Add addrspace parameters to memcpy lowering functions 2020-03-16 14:34:29 -04:00
Marcel Hlopko 7d382dcd46 [Syntax] Build declarator nodes
Summary:
Copy of https://reviews.llvm.org/D72089 with Ilya's permission. See
https://reviews.llvm.org/D72089 for the first batch of comments.

Reviewers: gribozavr2

Reviewed By: gribozavr2

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76220
2020-03-16 19:13:59 +01:00
Nico Weber 9e48422035 Revert "[llvm-objdump] Display locations of variables alongside disassembly"
Makes tests fail on Windows, see https://reviews.llvm.org/D70720#1924542

This reverts commit 3a5ddedadb, and
follow-ups:
f4cb9c919e
042eb0482a
c0cf5f5da9
18649f4813
f62b898c1f
2020-03-16 14:04:25 -04:00
Simon Pilgrim ebb181cf40 [X86] matchScalarReduction - add support for partial reductions
Add optional support for opt-in partial reduction cases by providing an optional partial mask to indicate which elements have been extracted for the scalar reduction.
2020-03-16 18:01:02 +00:00
Matt Arsenault 2e77362626 GlobalISel: Fix lower bswap for vectors
This would hit an assertion from trying to use the wrong bitwidth for
the constants.
2020-03-16 13:59:08 -04:00
Nemanja Ivanovic f594328853 [PowerPC] Disable sanitizer test due to failures when using LLD
This test case fails due to different handling of weak items between
LLD and LD on PPC. The issue only occurs when the default linker is LLD
and the test case is run on a system where ASLR is enabled.
2020-03-16 12:26:51 -05:00
Matt Arsenault 80b627d69d AMDGPU/GlobalISel: Fix handling of G_ANYEXT with s1 source
We were letting G_ANYEXT with a vcc register bank through, which was
incorrect and would select to an invalid copy. Fix this up like G_ZEXT
and G_SEXT. Also drop old code to fixup the non-boolean case in
RegBankSelect. We now have to perform that expansion during selection,
so there's no benefit to doing it during RegBankSelect.
2020-03-16 12:59:54 -04:00
Matt Arsenault c460dc6eeb AMDGPU/GlobalISel: Fix some illegal scalar argument types
Fixes integers that don't evenly divide to i32 pieces. We should
probably extract some of the code in the legalizer to start handling
argument breakdowns. I'm dissatisfied with the argument lowering's
handling of vectors for example, and we should not be producing the
weird G_EXTRACTs we do now.
2020-03-16 12:51:23 -04:00
Casey Carter 3609110967 Implement _LIBCPP_SUPPRESS_DEPRECATED_XXX when testing MSVC's STL
...to properly silence clang deprecation warnings in `test/std/utilities/meta/meta.trans/meta.trans.other/result_of11.pass.cpp`.
2020-03-16 09:50:23 -07:00
Tom Weaver 09f4bdc03f [DexTer] Add step.UNKNOWN check for NoneType line numbers.
Summary: It's possible for an instance of the visual studio debugger
to return a NoneType line number location when stepping during a
debugging session.

This patches teaches DexTer how to handle this particular case without
crashing out.

Reviewers: Orlando

Differential revision: https://reviews.llvm.org/D75992
2020-03-16 16:38:41 +00:00