Commit Graph

388475 Commits

Author SHA1 Message Date
Alexandros Lamprineas 1079870971 [llvm-mc][AArch64] HINT instruction disassembled as BTI
The Arm Architecture Reference Manual says that the SystemHintOp_BTI
opcode is prefered when CRm:op2 matches 0100:xx0, but llvm-mc
currently accepts 0100:xxx, which isn't right.

Differential Revision: https://reviews.llvm.org/D102415
2021-05-14 10:05:37 +01:00
Martin Storsjö c12c8124e1 [libcxx] [test] Change the generic_string_alloc test to test conversions to all char types
On windows, the native path char type is wchar_t - therefore, this test
didn't actually do the conversion that the test was supposed to exercise.

The charset conversions on windows do cause extra allocations outside of
the provided allocator though, so that bit of the test has to be waived
now that the test actually does something. (Other tests have similar
TEST_NOT_WIN32() for allocation checks for charset conversions.)

Also fix a typo, and amend the path.native.obs/string_alloc test to
test char8_t, too.

Differential Revision: https://reviews.llvm.org/D102360
2021-05-14 11:56:48 +03:00
Roman Lebedev 43a7f130a7
[X86] AMD Zen 3: same-reg AVX YMM VXORPD is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 11:56:07 +03:00
Roman Lebedev 336b9dbe88
[X86] AMD Zen 3: same-reg AVX XMM VXORPD is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 11:56:07 +03:00
Roman Lebedev 9c596bc541
[X86] AMD Zen 3: same-reg SSE XMM XORPD is a 1-cycle(!) dep-breaking zero-idiom
Same as with it's float friend, unlike their AVX versions.
As confirmed by exegesis, and ref docs.
2021-05-14 11:56:07 +03:00
Roman Lebedev 3567c7eda1
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VXORPD tests 2021-05-14 11:56:07 +03:00
Roman Lebedev 57eee56d0a
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VXORPD tests 2021-05-14 11:56:06 +03:00
Roman Lebedev fdc65e46b6
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM XORPD tests 2021-05-14 11:56:06 +03:00
Roman Lebedev 59554c01ab
[X86] AMD Zen 3: same-reg AVX YMM VXORPS is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis, and ref docs.
2021-05-14 11:56:06 +03:00
Roman Lebedev 2a7c52ff7f
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VXORPS tests 2021-05-14 11:56:06 +03:00
Roman Lebedev 26c1bffe67
[X86] AMD Zen 3: same-reg AVX XMM VXORPS is a zero-cycle(!) dep-breaking zero-idiom
Unlike it's legacy SSE XMM XORPS version, which measures as being 1-cycle,
this one is certainly a zero-cycle instruction, in addition to both of them
being dependency breaking.

As confirmed by exegesis measurements, and ref docs.
2021-05-14 11:56:06 +03:00
Roman Lebedev a9fb321a67
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VXORPS tests 2021-05-14 11:56:06 +03:00
Pooja Yadav 4763c8c9e3 [docs] Added llvm/cmake section
Added information about the cmake inside llvm.

Reviewed By: xgupta, jroelofs

Differential Revision: https://reviews.llvm.org/D101925
2021-05-14 14:10:56 +05:30
David Stuttard 31b62aa162 [AMDGPU] Fix codegen of image intrinsics for g16 and a16
For gfx10 gradient (g16) and address (a16) can be independent. Previous
implementation assumed that a16 implied g16.

There are some other changes that fix the verification (as well as asm/disasm)
that are required for the included test to pass - the XFAIL will be removed in
those changes.

This also includes required fixes for GlobalISel

Differential Revision: https://reviews.llvm.org/D102066

Change-Id: I7d171cc90994de05f41669b66a6d0ffa2ed05d09
2021-05-14 09:28:15 +01:00
David Stuttard 72d570ca08 [AMDGPU][AsmParser/Disassembler] Correct A16 and G16 handling
A16 support for image instructions assembly/disassembly (gfx10) was missing

Also refactor MIMG op addr size calcs to common function

We'd got 3 places where the same operation was being done.

One test is now marked XFAIL until a related codegen patch is in place

Differential Revision: https://reviews.llvm.org/D102231

Change-Id: I7e86e730ef8c71901457855cba570581f4f576bb
2021-05-14 09:25:44 +01:00
David Spickett 2db090a2eb [llvm][AsmPrinter] Restore source location to register clobber warning
Since 5de2d189e6 this particular warning
hasn't had the location of the source file containing the inline
assembly.

Fix this by reporting via LLVMContext. Which means that we no longer
have the "instantiated into assembly here" lines but they were going to
point to the start of the inline asm string anyway.

This message is already tested via IR in llvm. However we won't have
the required location info there so I've added a C file test in clang
to cover it.
(though strictly, this is testing llvm code)

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D102244
2021-05-14 08:22:57 +00:00
Alexey Bader 444f02d73c New tag for ittapi - fix an error related to cross-compiling ITTAPI in LLVM with mingw
Fix was implemented in the ittap repo to solve an error about cross-compiling ITTAPI in LLVM with mingw.
The problem occurred in the cross-compilation environment for Julia's dependencies.
The corresponding issue item in ittapi repo: https://github.com/intel/ittapi/issues/19
A new tag was created in ittapi repo for that fix.

This patch contains changes to update the ittapi tag in LLVM.

Reviewed By: bader

Differential Revision: https://reviews.llvm.org/D102471
2021-05-14 08:18:49 +03:00
dfukalov fdae3fc8b3 [GVN] Clobber partially aliased loads.
Use offsets stored in `AliasResult` implemented in D98718.

Updated with fix of issue reported in https://reviews.llvm.org/D95543#2745161

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D95543
2021-05-14 11:17:14 +03:00
David Green f7cb654763 [DSE] Move isOverwrite into DSEState. NFC
This moves the isOverwrite function into the DSEState so that it can
share the analyses and members from the state.

A few extra loop tests were also added to test stores in and around
multi block loops for D100464.
2021-05-14 09:16:51 +01:00
Lang Hames c82a0ae70e [ORC] Add JITLink dependence for ObjectLinkingLayerTest.
This aims to fix the failure at
https://lab.llvm.org/buildbot/#/builders/61/builds/9590.
2021-05-13 22:48:30 -07:00
LLVM GN Syncbot de115c3fb2 [gn build] Port 0fda4c4745 2021-05-14 04:56:03 +00:00
Lang Hames 0fda4c4745 [ORC] Add support for adding LinkGraphs directly to ObjectLinkingLayer.
This is separate from (but builds on) the support added in ec6b71df70 for
emitting LinkGraphs in the context of an active materialization. This commit
makes LinkGraphs a first-class data structure with features equivalent to
object files within ObjectLinkingLayer.
2021-05-13 21:44:13 -07:00
Lang Hames 9099c9ef78 [JITLink] Fix missing 'static' keyword in unit test. 2021-05-13 21:44:13 -07:00
Fangrui Song 261d6e05d5 [sanitizer] Simplify __sanitizer::BufferedStackTrace::UnwindImpl implementations
Intended to be NFC. D102046 relies on the refactoring for stack boundaries.
2021-05-13 21:26:31 -07:00
Carl Ritson 9cf6ff7aff [AMDGPU] Do not clause NSA instructions
To ensure correct behaviour NSA instructions should not be claused.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D102211
2021-05-14 12:54:56 +09:00
Reid Kleckner d2f4b7d778 Use enum comparison instead of generated switch/case, NFC
Clang's coverage data for auto-generated switch cases is really, really
large. Before this change, when I enable code coverage, SemaDeclAttr.obj
is 4.0GB. Naturally, this fails to link.

Replacing the RISCV builtin id check with a comparison reduces object
file size from 4.0GB to 330MB. Replacing the AArch64 SVE range check
reduces the size again down to 17MB, which is reasonable.

I think the RISCV switch is larger in coverage data because it uses more
levels of macro expansion, while the SVE intrinsics only use one. In any
case, please try to avoid switches with 1000+ cases, they usually don't
optimize well.
2021-05-13 20:26:50 -07:00
Reid Kleckner ee23f8b36f [COFF] Remove a truncation assertion from setRVA
LLD already produces a nice error message when sections exceed 4GB, and
this setRVA assertion causes LLD to crash instead of diagnosing the
error properly.

No test because we don't want slow tests that create 4GB files.
2021-05-13 19:37:14 -07:00
Matthias Springer a088bed4e3 [mlir] VectorToSCF cleanup
Group functions/structs in namespaces for better code readability.

Depends On D102123

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102124
2021-05-14 11:04:37 +09:00
Rahul Joshi 23a84e1c60 [MLIR] Fix build failures due to unused variables in non-debug builds.
Differential Revision: https://reviews.llvm.org/D102458
2021-05-13 18:42:48 -07:00
Lang Hames 65736ac439 [ORC] Remove the OrcExecutionTest class. It is no longer used. 2021-05-13 18:32:36 -07:00
Lang Hames 527bd6dc1c [ORC] Remove unused RTDyldObjectLinkingLayerExecutionTest class from unit test. 2021-05-13 18:32:35 -07:00
Lang Hames c76e3c319e [ORC] Remove some stale unit test utils.
This code was used to test ORCv1, which has been removed. It is not useful for
testing ORCv2.
2021-05-13 18:32:35 -07:00
Matthias Springer 2ca887de6e [mlir] VectorToSCF target rank is a pass option
Make "target rank" a pass option of VectorToSCF.

Depends On D102101

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102123
2021-05-14 10:30:43 +09:00
Chen Zheng 61484762e9 [Debug-Info] change Tag type to dwarf::Tag for createAndAddDIE; NFC
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102207
2021-05-13 21:15:06 -04:00
Peter Collingbourne f79929acea scudo: Fix MTE error reporting for zero-sized allocations.
With zero-sized allocations we don't actually end up storing the
address tag to the memory tag space, so store it in the first byte of
the chunk instead so that we can find it later in getInlineErrorInfo().

Differential Revision: https://reviews.llvm.org/D102442
2021-05-13 18:14:03 -07:00
Peter Collingbourne 9567131d03 scudo: Check for UAF in ring buffer before OOB in more distant blocks.
It's more likely that we have a UAF than an OOB in blocks that are
more than 1 block away from the fault address, so the UAF should
appear first in the error report.

Differential Revision: https://reviews.llvm.org/D102379
2021-05-13 18:14:02 -07:00
Arthur Eubanks ab6a609d96 [test] Fix new-pm-lto-defaults.ll to work on all platforms
https://lab.llvm.org/buildbot/#/builders/119/builds/3775/steps/8/logs/FAIL__LLVM__new-pm-lto-defaults_ll

Followup to D102345.
2021-05-13 18:12:55 -07:00
H.J. Lu 72797dedb7 [sanitizer] Use size_t on g_tls_size to fix build on x32
On x32 size_t == unsigned int, not unsigned long int:

../../../../../src-master/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp: In function ??void __sanitizer::InitTlsSize()??:
../../../../../src-master/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp:209:55: error: invalid conversion from ??__sanitizer::uptr*?? {aka ??long unsigned int*??} to ??size_t*?? {aka ??unsigned int*??} [-fpermissive]
  209 |   ((void (*)(size_t *, size_t *))get_tls_static_info)(&g_tls_size, &tls_align);
      |                                                       ^~~~~~~~~~~
      |                                                       |
      |                                                       __sanitizer::uptr* {aka long unsigned int*}

by using size_t on g_tls_size.  This is to fix:

https://bugs.llvm.org/show_bug.cgi?id=50332

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D102446
2021-05-13 18:07:11 -07:00
Chen Zheng 75f3beeedf [Debug-Info] make DIE attributes generation under strict DWARF control
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D101024
2021-05-13 20:34:07 -04:00
Amara Emerson af6eb1c710 [AArch64][GlobalISel] Fix a crash during unsuccessful G_CTPOP <2 x s64> legalization.
The legalization rule for scalar-same-as doesn't handle vectors. Until we
implement custom legalization for this, at least fall back properly.
2021-05-13 17:28:11 -07:00
Valentin Clement 8fdfead71a [mlir][openacc][NFC] add anonymous namespace around LegalizeDataOpForLLVMTranslation class
Add missing anonymous namespace around LegalizeDataOpForLLVMTranslation class .

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102380
2021-05-13 20:27:59 -04:00
Reid Kleckner 5ba4a0e890 [gn] Don't pass -fprofile-instr-generate to linker on Windows
Avoids a warning from the linker. The user still has to put the resource
directory on the linker search path, and I can't find a clean way to do
that automatically in gn.
2021-05-13 16:04:11 -07:00
Matt Arsenault 85394d9ed7 AMDGPU/GlobalISel: Don't hardcode stack alignment in assert message 2021-05-13 19:00:13 -04:00
Matt Arsenault 6a70874d27 AMDGPU/GlobalISel: Implement tail calls
Or at least the sibling call cases which the DAG already handles.
2021-05-13 18:57:42 -04:00
Nicolas Vasilache bebf5d56bf [mlir][Linalg] Add support for vector.transfer ops to comprehensive bufferization (2/n).
Differential revision: https://reviews.llvm.org/D102395
2021-05-13 22:26:28 +00:00
Nicolas Vasilache 1e01a8919f [mlir][Linalg] Add ComprehensiveBufferize for functions(step 1/n)
This is the first step towards upstreaming comprehensive bufferization following the
discourse post: https://llvm.discourse.group/t/rfc-linalg-on-tensors-update-and-comprehensive-bufferization-rfc/3373/6.

This first commit introduces a basic pass for bufferizing within function boundaries,
assuming that the inplaceable function boundaries have been marked as such.

Differential revision: https://reviews.llvm.org/D101693
2021-05-13 22:24:40 +00:00
Weston Carvalho be5c7c5d82 Widen `name` stencil to support `TypeLoc` nodes.
Differential Revision: https://reviews.llvm.org/D102185
2021-05-13 23:23:12 +01:00
Arthur Eubanks 2155dc51d7 [IR] Introduce the opaque pointer type
The opaque pointer type is essentially just a normal pointer type with a
null pointee type.

This also adds support for the opaque pointer type to the bitcode
reader/writer, as well as to textual IR.

To avoid confusion with existing pointer types, we disallow creating a
pointer to an opaque pointer.

Opaque pointer types should not be widely used at this point since many
parts of LLVM still do not support them. The next steps are to add some
very simple use cases of opaque pointers to make sure they work, then
start pretending that all pointers are opaque pointers and see what
breaks.

https://lists.llvm.org/pipermail/llvm-dev/2021-May/150359.html

Reviewed By: dblaikie, dexonsmith, pcc

Differential Revision: https://reviews.llvm.org/D101704
2021-05-13 15:22:27 -07:00
Michael Kruse 83ff0ff463 [Clang][OpenMP] Allow unified_shared_memory for Pascal-generation GPUs.
The Pascal architecture supports the page migration engine required for
unified_shared_memory, as indicated by NVIDIA:
 * https://developer.nvidia.com/blog/unified-memory-cuda-beginners/
 * https://developer.nvidia.com/blog/beyond-gpu-memory-limits-unified-memory-pascal/
 * https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#um-requirements

The limitation was introduced in D54493 which justified the cut-off by
the requirement for unified addressing. However, Unified Virtual
Addressing (UVA) is already available with sm20 (Fermi, Kepler,
Maxwell):
 * https://docs.nvidia.com/cuda/gpudirect-rdma/index.html#basics-of-uva-cuda-memory-management

Unified shared memory might even be possible with these, but with
migration of entire allocations on kernel startup.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D101595
2021-05-13 17:15:34 -05:00
cynecx 93d56922fa Don't run MachineVerifier on sjlj-unwind-inline-asm test because of known issue (PR39439)
Fixes buildbot failure (https://lab.llvm.org/buildbot/#/builders/16/builds/10825).

Reviewed By: Amanieu

Differential Revision: https://reviews.llvm.org/D102433
2021-05-13 23:14:05 +01:00