Commit Graph

5560 Commits

Author SHA1 Message Date
Ian Bearman 0816b96a10 Allow same memory space for SRC and DST of dma_start operations
This change allows the SRC and DST of dma_start operations to be located in the
    same memory space. This applies to both the Affine dialect and Memref dialect
    versions of these Ops. The documention has been updated to reflect this by
    explicitly stating overlapping memory locations are not supported (undefined
    behavior).

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D102274
2021-05-14 10:40:15 -07:00
Matthias Springer a088bed4e3 [mlir] VectorToSCF cleanup
Group functions/structs in namespaces for better code readability.

Depends On D102123

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102124
2021-05-14 11:04:37 +09:00
Rahul Joshi 23a84e1c60 [MLIR] Fix build failures due to unused variables in non-debug builds.
Differential Revision: https://reviews.llvm.org/D102458
2021-05-13 18:42:48 -07:00
Matthias Springer 2ca887de6e [mlir] VectorToSCF target rank is a pass option
Make "target rank" a pass option of VectorToSCF.

Depends On D102101

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102123
2021-05-14 10:30:43 +09:00
Valentin Clement 8fdfead71a [mlir][openacc][NFC] add anonymous namespace around LegalizeDataOpForLLVMTranslation class
Add missing anonymous namespace around LegalizeDataOpForLLVMTranslation class .

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102380
2021-05-13 20:27:59 -04:00
Nicolas Vasilache bebf5d56bf [mlir][Linalg] Add support for vector.transfer ops to comprehensive bufferization (2/n).
Differential revision: https://reviews.llvm.org/D102395
2021-05-13 22:26:28 +00:00
Nicolas Vasilache 1e01a8919f [mlir][Linalg] Add ComprehensiveBufferize for functions(step 1/n)
This is the first step towards upstreaming comprehensive bufferization following the
discourse post: https://llvm.discourse.group/t/rfc-linalg-on-tensors-update-and-comprehensive-bufferization-rfc/3373/6.

This first commit introduces a basic pass for bufferizing within function boundaries,
assuming that the inplaceable function boundaries have been marked as such.

Differential revision: https://reviews.llvm.org/D101693
2021-05-13 22:24:40 +00:00
Rob Suderman f97d970a49 [mlir][tosa] Add lowering to tosa.abs for integer cases
Integer case requires decomposing to simple LLVM operatons.

Differential Revision: https://reviews.llvm.org/D101809
2021-05-13 13:55:17 -07:00
natashaknk 0831793ed9 [mlir][tosa] Add tosa.div integer lowering to linalg.generic.
Lowering div elementwise op to the linalg dialect. Since tosa only supports integer division, that is the only version that is currently implemented.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D102430
2021-05-13 13:16:00 -07:00
Sean Silva 12874e93a1 [mlir][NFC] Add helper for common pattern of replaceAllUsesExcept
This covers the extremely common case of replacing all uses of a Value
with a new op that is itself a user of the original Value.

This should also be a little bit more efficient than the
`SmallPtrSet<Operation *, 1>{op}` idiom that was being used before.

Differential Revision: https://reviews.llvm.org/D102373
2021-05-13 12:42:10 -07:00
Weiwei Li cd0eeb52ad [mlir][spirv] Define spv.ImageQuerySize operation
Support OpImageQuerySize in spirv dialect

co-authored-by: Alan Liu <alanliu.yf@gmail.com>

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D102029
2021-05-13 13:17:08 -04:00
Tobias Gysi cf194da1bb [mlir][linalg] Remove IndexedGenericOp support from FusionOnTensors...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102163
2021-05-13 14:57:16 +00:00
Matthias Springer 0f24163870 [mlir] Replace vector-to-scf with progressive-vector-to-scf
Depends On D102388

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102101
2021-05-13 23:27:31 +09:00
Tobias Gysi f358c37209 [mlir][linalg] Remove IndexedGenericOp support from DropUnitDims...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102235
2021-05-13 14:18:59 +00:00
Matthias Springer d020dd2b21 [mlir] Migrate vector-to-loops.mlir to ProgressiveVectorToSCF
Create a copy of vector-to-loops.mlir and adapt the test for
ProgressiveVectorToSCF. Fix a small bug in getExtractOp() triggered by
this test.

Differential Revision: https://reviews.llvm.org/D102388
2021-05-13 22:48:20 +09:00
Matthias Springer bf068e1077 [mlir] Do not use pass labels in unrolled ProgressiveVectorToSCF
Do not rely on pass labels to detect if the pattern was already applied in the past (which allows for more some extra optimizations to avoid extra InsertOps and ExtractOps). Instead, check if these optimizations can be applied on-the-fly.

This also fixes a bug, where vector.insert and vector.extract ops sometimes disappeared in the middle of the pass because they get folded away, but the next application of the pattern expected them to be there.

Differential Revision: https://reviews.llvm.org/D102206
2021-05-13 22:01:08 +09:00
Matthias Springer 60da33c2d4 [mlir] Support masks in TransferOpReduceRank and TransferReadPermutationLowering
These two patterns allow for more efficient codegen in VectorToSCF.

Differential Revision: https://reviews.llvm.org/D102222
2021-05-13 15:08:08 +09:00
Rob Suderman 3f8aafd790 [mlir][tosa] Fix tosa.cast semantics to perform rounding/clipping
Rounding to integers requires rounding (for floating points) and clipping
to the min/max values of the destination range. Added this behavior and
updated tests appropriately.

Reviewed By: sjarus, silvas

Differential Revision: https://reviews.llvm.org/D102375
2021-05-12 21:53:53 -07:00
Matthias Springer 2a51e9ff2e [mlir] Support memref layout maps in vector transfer ops
Differential Revision: https://reviews.llvm.org/D102042
2021-05-13 13:22:21 +09:00
Matthias Springer 9b77be5583 [mlir] Unrolled progressive-vector-to-scf.
Instead of an SCF for loop, these pattern generate fully unrolled loops with no temporary buffer allocations.

Differential Revision: https://reviews.llvm.org/D101981
2021-05-13 13:08:48 +09:00
Matthias Springer 864adf399e [mlir] Allow empty position in vector.insert and vector.extract
Such ops are no-ops and are folded to their respective `source`/`vector` operand.

Differential Revision: https://reviews.llvm.org/D101879
2021-05-13 12:54:18 +09:00
Matthias Springer c52cbe63e4 [mlir] Fix masked vector transfer ops with broadcasts
Broadcast dimensions of a vector transfer op have no corresponding dimension in the mask vector. E.g., a 2-D TransferReadOp, where one dimension is a broadcast, can have a 1-D `mask` attribute.

This commit also adds a few additional transfer op integration tests for various combinations of broadcasts, masking, dim transposes, etc.

Differential Revision: https://reviews.llvm.org/D101745
2021-05-13 12:46:03 +09:00
Matthias Springer 6555e53ab0 Revert "[mlir] Fix masked vector transfer ops with broadcasts"
This reverts commit c9087788f7.

Accidentally pushed old version of the commit.
2021-05-13 11:55:00 +09:00
Matthias Springer c9087788f7 [mlir] Fix masked vector transfer ops with broadcasts
Broadcast dimensions of a vector transfer op have no corresponding dimension in the mask vector. E.g., a 2-D TransferReadOp, where one dimension is a broadcast, can have a 1-D `mask` attribute.

This commit also adds a few additional transfer op integration tests for various combinations of broadcasts, masking, dim transposes, etc.

Differential Revision: https://reviews.llvm.org/D101745
2021-05-13 11:37:36 +09:00
Aart Bik 58d12332a4 [mlir][sparse][capi][python] add sparse tensor passes
First set of "boilerplate" to get sparse tensor
passes available through CAPI and Python.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D102362
2021-05-12 16:40:50 -07:00
Eugene Zhulenev fb3a00c327 [mlir] Fix ssa values naming bug
Address comments in https://reviews.llvm.org/D102226 to fix the bug + style violations

Differential Revision: https://reviews.llvm.org/D102368
2021-05-12 14:30:29 -07:00
River Riddle 29ac15ab38 [mlir-lsp-server][NFC] Add newline between Protocol JSON serialization methods and class definitions. 2021-05-12 13:02:25 -07:00
River Riddle b3911cdfc8 [mlir-lsp-server] Add support for sending diagnostics to the client
This allows for diagnostics emitted during parsing/verification to be surfaced to the user by the language client, as opposed to just being emitted to the logs like they are now.

Differential Revision: https://reviews.llvm.org/D102293
2021-05-12 13:02:25 -07:00
Suraj Sudhir 4b01435230 [mlir][tosa] Remove tosa.identityn operator
Removes the identityn operator from TOSA MLIR definition.
Removes TosaToLinAlg mappings

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D102329
2021-05-12 12:46:22 -07:00
Rob Suderman 7b57517507 [mlir][linalg] Fixed issue generating reassociation map with Rank-0 types
Rank-0 case causes a graph during linalg reshape operation.

Differential Revision: https://reviews.llvm.org/D102282
2021-05-12 11:00:51 -07:00
Valentin Clement 113b807017 [mlir][openacc] Add OpenACC translation to LLVM IR (enter_data op create/copyin)
This patch begins to translate acc.enter_data operation to call to tgt runtime call.
It currently only translate create/copyin operands of memref type. This acts as a basis to add support
for FIR types in the Flang/OpenACC support. It follows more or less a similar path than clang
with `omp target enter data map` directives.
This patch is taking a different approach than D100678 and perform a translation to LLVM IR
and make use of the OpenMPIRBuilder instead of doing a conversion to the LLVMIR dialect.

OpenACC support in Flang will rely on the current OpenMP runtime where 1:1 lowering can be
applied. Some extension will be added where features are not available yet.

Big part of this code will be shared for other standalone data operations in the OpenACC
dialect such as acc.exit_data and acc.update.

It is likely that parts of the lowering can also be shared later with the ops for
standalone data directives in the OpenMP dialect when they are introduced.

This is an initial translation and it probably needs more work.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D101504
2021-05-12 13:41:14 -04:00
Inho Seo 5480ea6c84 Update static bound checker for Linalg to cover decreasing cases
The current static checker for linalg does not work on the decreasing
index cases well. So, this is to Update the current static bound checker
for linalg to cover decreasing index cases.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D102302
2021-05-12 10:29:19 -07:00
Aart Bik ca5d0a7310 [mlir][sparse] keep runtime support library signature consistent
Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D102285
2021-05-12 09:59:46 -07:00
Fabian Schuiki 33f908c428
[MLIR] Factor pass timing out into a dedicated timing manager
This factors out the pass timing code into a separate `TimingManager`
that can be plugged into the `PassManager` from the outside. Users are
able to provide their own implementation of this manager, and use it to
time additional code paths outside of the pass manager. Also allows for
multiple `PassManager`s to run and contribute to a single timing report.

More specifically, moves most of the existing infrastructure in
`Pass/PassTiming.cpp` into a new `Support/Timing.cpp` file and adds a
public interface in `Support/Timing.h`. The `PassTiming` instrumentation
becomes a wrapper around the new timing infrastructure which adapts the
instrumentation callbacks to the new timers.

Reviewed By: rriddle, lattner

Differential Revision: https://reviews.llvm.org/D100647
2021-05-12 18:14:51 +02:00
Valentin Clement 6110b667b0 [mlir][openacc] Conversion of data operand to LLVM IR dialect
Add a conversion pass to convert higher-level type before translation.
This conversion extract meangingful information and pack it into a struct that
the translation (D101504) will be able to understand.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D102170
2021-05-12 11:34:15 -04:00
Tobias Gysi 06bb9cf30d [mlir][linalg] Remove IndexedGenericOp support from LinalgInterchangePattern...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102245
2021-05-12 13:01:37 +00:00
Tobias Gysi c6b96ae06f [mlir][linalg] Remove IndexedGenericOp support from LinalgBufferize...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102308
2021-05-12 12:15:05 +00:00
Tobias Gysi 0fb364a97e [mlir][linalg] Remove IndexedGenericOp support from LinalgToStandard...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102236
2021-05-12 11:56:07 +00:00
Ulysse Beaugnon 27b2bd7601 [MLIR] Enable conversion from llvm::SMLoc to mlir::Location with OpAsmParser.
DialectAsmParser already allows converting an llvm::SMLoc location to a
mlir::Location location. This commit adds the same functionality to OpAsmParser.
Implementation is copied from DialectAsmParser.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102165
2021-05-12 09:08:32 +02:00
Dumitru Potop 9a0ea5994b [mlir] Support alignment in LLVM dialect GlobalOp
First step in adding alignment as an attribute to MLIR global definitions. Alignment can be specified for global objects in LLVM IR. It can also be specified as a named attribute in the LLVMIR dialect of MLIR. However, this attribute has no standing and is discarded during translation from MLIR to LLVM IR. This patch does two things: First, it adds the attribute to the syntax of the llvm.mlir.global operation, and by doing this it also adds accessors and verifications. The syntax is "align=XX" (with XX being an integer), placed right after the value of the operation. Second, it allows transforming this operation to and from LLVM IR. It is checked whether the value is an integer power of 2.

Reviewed By: ftynse, mehdi_amini

Differential Revision: https://reviews.llvm.org/D101492
2021-05-12 09:07:20 +02:00
Chia-hung Duan f653313d4a [mlir][AsmPrinter] Remove recursion while SSA naming
Address the TODO of removing recursion while SSA naming.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D102226
2021-05-12 11:23:01 +08:00
Rob Suderman 764ad3b3fa [mlir][tosa] Tosa elementwise broadcasting had some minor bugs
Updated tests to include broadcast of left and right. Includes
bypass if in-type and out-type match shape (no broadcasting).

Differential Revision: https://reviews.llvm.org/D102276
2021-05-11 13:58:06 -07:00
River Riddle a9bbbaaa88 [mlir] Elide large elements attrs when printing Operations in diagnostics
Diagnostics are intended to be read by users, and in most cases displayed in a terminal. When not eliding huge element attributes, in some cases we end up dumping hundreds of megabytes(gigabytes) to the terminal (or logs), completely obfuscating the main diagnostic being shown.

Differential Revision: https://reviews.llvm.org/D102272
2021-05-11 13:50:27 -07:00
Sean Silva 49755871ad [mlir][ODS]: Add per-op cppNamespace.
This is useful for dialects that have logical subparts.

Differential Revision: https://reviews.llvm.org/D102200
2021-05-11 10:48:05 -07:00
Benjamin Kramer b20e150c9b [mlir] Use static shape knowledge when lowering memref.reshape
This is actually necessary for correctness, as memref.reinterpret_cast
doesn't verify if the output shape doesn't match the static sizes.

Differential Revision: https://reviews.llvm.org/D102232
2021-05-11 18:21:09 +02:00
Uday Bondhugula 1c777ab459 [MLIR] Switch llvm.noalias to a unit attribute
Switch llvm.noalias attribute from a boolean attribute to a unit
attribute.

Differential Revision: https://reviews.llvm.org/D102225
2021-05-11 15:41:09 +05:30
Tres Popp 88a48999d2 Support VectorTransfer splitting on writes also.
VectorTransfer split previously only split read xfer ops. This adds
the same logic to write ops. The resulting code involves 2
conditionals for write ops while read ops only needed 1, but the created
ops are built upon the same patterns, so pattern matching/expectations
are all consistent other than in regards to the if/else ops.

Differential Revision: https://reviews.llvm.org/D102157
2021-05-11 10:33:27 +02:00
Tobias Gysi 7bc6df2528 [mlir][linalg] Remove IndexedGenericOp support from LinalgToLoops...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102187
2021-05-11 06:53:47 +00:00
Tobias Gysi 6676e09b22 [mlir][linalg] Remove IndexedGenericOp support from Fusion...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102174
2021-05-11 06:49:25 +00:00
Tobias Gysi d69bccf1ed [mlir][linalg] Remove IndexedGenericOp support from Tiling...
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102176
2021-05-11 05:53:58 +00:00