efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
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Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
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llvm-svn: 140413
2011-09-23 21:02:01 +00:00
7591d0c363
Thumb2 register-shifted-register loads cannot target the PC or the SP.
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llvm-svn: 140412
2011-09-23 21:00:32 +00:00
163be01d69
tMOVSr is not allowed in an IT block either.
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llvm-svn: 140104
2011-09-19 23:57:20 +00:00
61e4604dd8
CPS instructions are UNPREDICTABLE inside IT blocks.
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llvm-svn: 140102
2011-09-19 23:47:10 +00:00
f902d92fc9
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
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llvm-svn: 140079
2011-09-19 22:34:23 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
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llvm-svn: 140078
2011-09-19 22:21:13 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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llvm-svn: 140032
2011-09-19 18:07:10 +00:00
502cd9d87a
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
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llvm-svn: 139972
2011-09-16 23:30:01 +00:00
b925e935d7
Fix bitfield decoding based on Eli's feedback.
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llvm-svn: 139969
2011-09-16 23:04:48 +00:00
bcfa9a6f89
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
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llvm-svn: 139965
2011-09-16 22:42:36 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
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llvm-svn: 139964
2011-09-16 22:29:48 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
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llvm-svn: 139943
2011-09-16 21:08:33 +00:00
a0c3b97221
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
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llvm-svn: 139876
2011-09-15 23:38:46 +00:00
f1e384421a
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
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llvm-svn: 139736
2011-09-14 21:06:21 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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llvm-svn: 139522
2011-09-12 18:56:30 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
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llvm-svn: 139432
2011-09-09 23:13:33 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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llvm-svn: 139422
2011-09-09 22:24:36 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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llvm-svn: 139415
2011-09-09 21:48:23 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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llvm-svn: 139381
2011-09-09 18:37:27 +00:00
33d39536e6
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
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llvm-svn: 139329
2011-09-08 22:48:37 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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llvm-svn: 139328
2011-09-08 22:42:49 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
f174959286
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
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llvm-svn: 139268
2011-09-08 00:11:18 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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llvm-svn: 139256
2011-09-07 21:10:42 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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llvm-svn: 139240
2011-09-07 17:55:19 +00:00
4c493e8050
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
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llvm-svn: 139237
2011-09-07 17:24:38 +00:00
ed96b58bd2
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
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llvm-svn: 138982
2011-09-01 23:35:51 +00:00
03aadae01f
Fix 80 columns violations.
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llvm-svn: 138980
2011-09-01 23:23:50 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
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llvm-svn: 138948
2011-09-01 18:02:14 +00:00
4af0aa98d5
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
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llvm-svn: 138910
2011-08-31 22:00:41 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
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llvm-svn: 138840
2011-08-30 22:58:27 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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llvm-svn: 138675
2011-08-26 23:32:08 +00:00
240d20af79
Spelling fail.
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llvm-svn: 138667
2011-08-26 21:47:57 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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llvm-svn: 138653
2011-08-26 20:43:14 +00:00
5658b49f64
Update for feedback from Jim.
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llvm-svn: 138642
2011-08-26 19:39:26 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
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This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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llvm-svn: 138635
2011-08-26 18:09:22 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
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This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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llvm-svn: 138575
2011-08-25 18:30:18 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
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llvm-svn: 138507
2011-08-24 22:40:22 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
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llvm-svn: 138492
2011-08-24 21:35:46 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
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llvm-svn: 138443
2011-08-24 17:21:43 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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llvm-svn: 138341
2011-08-23 17:51:38 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
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llvm-svn: 138339
2011-08-23 17:45:18 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
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llvm-svn: 138306
2011-08-22 23:44:04 +00:00
Jim Grosbach