0c6cb46ac1
add a note
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llvm-svn: 126719
2011-03-01 00:24:51 +00:00
49d15b959e
Unbreak CMake build.
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llvm-svn: 126717
2011-03-01 00:02:51 +00:00
20164dcc68
Unbreak CMake build.
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llvm-svn: 126715
2011-02-28 23:56:33 +00:00
3a0a30d44d
Add an END_WITH_NULL accessor for ConstantStruct.
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llvm-svn: 126714
2011-02-28 23:53:27 +00:00
1ac5e0c5c6
update cmake
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llvm-svn: 126694
2011-02-28 22:45:25 +00:00
ec0fc7d842
Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931
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llvm-svn: 126689
2011-02-28 22:04:27 +00:00
63b0d108a2
Add missing whitespace in the formatting.
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llvm-svn: 126687
2011-02-28 21:45:12 +00:00
30a52dec93
Make all static functions become static class methods. Move shared (duplicated) functions to new MCELF class.
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llvm-svn: 126686
2011-02-28 21:45:04 +00:00
0dc63104c6
Use the correct shift amount type.
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llvm-svn: 126684
2011-02-28 21:10:10 +00:00
4f4df81861
Clean whitespace.
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llvm-svn: 126683
2011-02-28 20:57:56 +00:00
c93d207e8c
fix a signed comparison warning.
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llvm-svn: 126682
2011-02-28 20:50:35 +00:00
06d70015ce
Delete the GEPSplitter experiment.
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llvm-svn: 126671
2011-02-28 19:47:47 +00:00
b8a25f49f3
Delete the SimplifyHalfPowrLibCalls pass, which was unused, and
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only existed as the result of a misunderstanding.
llvm-svn: 126669
2011-02-28 19:41:14 +00:00
161058838c
Delete the LiveValues pass. I won't get get back to the project it
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was started for in the foreseeable future.
llvm-svn: 126668
2011-02-28 19:37:59 +00:00
20a1cbefad
[AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit
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and 256-bit forms. Because the number of elements in a vector
does not determine the vector type (4 elements could be v4f32 or
v4f64), pass the full type of the vector to decode routines.
llvm-svn: 126664
2011-02-28 19:06:56 +00:00
58775fea6f
Fix the arm's disassembler for blx that was building an MCInst without the
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needed two predicate operands before the imm operand.
llvm-svn: 126662
2011-02-28 18:46:31 +00:00
6e3d443646
Fix a typo which cause dag combine crash. rdar://9059537.
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llvm-svn: 126661
2011-02-28 18:45:27 +00:00
67c5c3e939
Support for byval parameters on ARM. Will be enabled by a forthcoming
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patch to the front-end. Radar 7662569.
llvm-svn: 126655
2011-02-28 17:17:53 +00:00
612b85e58c
Add branch hinting for SPU.
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The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.
llvm-svn: 126651
2011-02-28 14:08:24 +00:00
8ae07996c9
Teach SimplifyCFG that (switch (select cond, X, Y)) is better expressed as a branch.
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Based on a patch by Alistair Lynn.
llvm-svn: 126647
2011-02-28 09:44:07 +00:00
afe4a3062d
Fix comment.
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llvm-svn: 126645
2011-02-28 09:18:11 +00:00
66f4f22f7b
srem doesn't actually have the same resulting sign as its numerator, you could
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also have a zero when numerator = denominator. Reverts parts of r126635 and
r126637.
llvm-svn: 126644
2011-02-28 09:17:39 +00:00
174a705497
Teach InstCombine to fold "(shr exact X, Y) == 0" --> X == 0, fixing #1 from
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PR9343.
llvm-svn: 126643
2011-02-28 08:31:40 +00:00
c9aab8567b
Teach value tracking to make use of flags in more situations.
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llvm-svn: 126642
2011-02-28 08:02:21 +00:00
29dbbd12c1
Teach ValueTracking to look at the dividend when determining the sign bit of an
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srem instruction.
llvm-svn: 126637
2011-02-28 06:52:12 +00:00
75a800d3bf
Add preliminary support for .f32 in the PTX backend.
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- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
to accept the float type.
- Add appropriate test cases.
Patch by Justin Holewinski
llvm-svn: 126636
2011-02-28 06:34:09 +00:00
6b445419b0
The sign of an srem instruction is the sign of its dividend (the first
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argument), regardless of the divisor. Teach instcombine about this and fix
test7 in PR9343!
llvm-svn: 126635
2011-02-28 06:20:05 +00:00
25bddae404
Silence enum conversion warnings.
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llvm-svn: 126578
2011-02-27 18:13:53 +00:00
f571290d1e
Legalize support for fpextend of vector. PR9309.
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llvm-svn: 126574
2011-02-27 14:41:27 +00:00
d4e5003a3f
Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs.
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It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).
llvm-svn: 126568
2011-02-27 08:47:19 +00:00
b00913028f
Fix typos in the comments.
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llvm-svn: 126565
2011-02-27 07:40:43 +00:00
98eecaf0a9
RegionPrinter: Ignore back edges when layouting the graph
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llvm-svn: 126564
2011-02-27 04:11:07 +00:00
3ac8689fa3
Pass the graph to the DOTGraphTraits.getEdgeAttributes().
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This follows the interface of getNodeAttributes.
llvm-svn: 126562
2011-02-27 04:11:03 +00:00
06dfe8e9c5
Support: Add llvm::AreStatisticsEnabled().
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llvm-svn: 126558
2011-02-26 23:17:12 +00:00
26691d9660
Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.
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1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible
It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.
llvm-svn: 126557
2011-02-26 22:48:07 +00:00
416c47019c
Trailing whitespace.
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llvm-svn: 126526
2011-02-25 22:53:20 +00:00
b2c80da4ae
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
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llvm-svn: 126518
2011-02-25 21:41:48 +00:00
fcf51fd298
Roll out r126425 and r126450 to see if it fixes the failures on the buildbots.
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llvm-svn: 126488
2011-02-25 16:30:32 +00:00
ceb5daa567
Revert "SimplifyCFG: GEPs with just one non-constant index are also cheap."
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Yes, there are other types than i8* and GEPs on them can produce an add+multiply.
We don't consider that cheap enough to be speculatively executed.
llvm-svn: 126481
2011-02-25 10:33:33 +00:00
e3ecd5fb9b
Add patterns to use post-increment addressing for Neon VST1-lane instructions.
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llvm-svn: 126477
2011-02-25 06:42:42 +00:00
14a07365cb
Fix formatting of debug helper string.
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llvm-svn: 126471
2011-02-25 03:59:03 +00:00
a921dc5860
Fix typo.
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llvm-svn: 126467
2011-02-25 01:29:29 +00:00
4c82cd21ed
Set NumSignBits to 1 if KnownZero/KnownOne are being zero extended. In theory it
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is possible to do better if the high bit is set in either KnownZero/KnownOne, but
in practice NumSignBits is always 1 when we are zero extending because nothing
is known about that register.
llvm-svn: 126465
2011-02-25 01:11:01 +00:00
d2f3041c7f
We only want to zero extend the existing information if the bit width is
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actually larger.
llvm-svn: 126464
2011-02-25 01:10:55 +00:00
9918b33451
Try harder to get the hint by preferring to evict hint interference.
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llvm-svn: 126463
2011-02-25 01:04:22 +00:00
70d29634a9
Each prologue may have multiple vpush instructions to store callee-saved
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D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.
Sorry, can't reduce a small test case.
rdar://9043312
llvm-svn: 126457
2011-02-25 00:24:46 +00:00
dfdca1a14d
SimplifyCFG: GEPs with just one non-constant index are also cheap.
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llvm-svn: 126452
2011-02-24 23:26:09 +00:00
e68a27eecd
Tweak the register allocator priority queue some more.
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New live ranges are assigned in long -> short order, but live ranges that have
been evicted at least once are deferred and assigned in short -> long order.
Also disable splitting and spilling for live ranges seen for the first time.
The intention is to create a realistic interference pattern from the heavy live
ranges before starting splitting and spilling around it.
llvm-svn: 126451
2011-02-24 23:21:36 +00:00
1db7b187cb
Remove dead variable.
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llvm-svn: 126450
2011-02-24 23:15:43 +00:00
27361a7124
SimplifyCFG: GEPs with constant indices are cheap enough to be executed unconditionally.
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llvm-svn: 126445
2011-02-24 22:46:11 +00:00
Chris Lattner