Commit Graph

276634 Commits

Author SHA1 Message Date
Sander de Smalen 0c5a29b6be [AArch64][TableGen] Skip tied result operands for InstAlias
Summary:
This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias.

This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests.

Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch.


Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka

Reviewed By: rengolin, SjoerdMeijer

Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D40030

llvm-svn: 318650
2017-11-20 14:36:40 +00:00
Valery Pykhtin f2fe9725ea AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
Differential revision: https://reviews.llvm.org/D39897

llvm-svn: 318649
2017-11-20 14:35:53 +00:00
Peter Smith 931c9fa8fe [ARM] For assembler files recognize -Xassembler or -Wa, -mthumb
Attempt to fix warning picked up by buildbot.

llvm-svn: 318648
2017-11-20 13:53:55 +00:00
Peter Smith 3947cb3cf0 [ARM] For assembler files recognize -Xassembler or -Wa, -mthumb
The Unified Arm Assembler Language is designed so that the majority of
assembler files can be assembled for both Arm and Thumb with the choice
made as a compilation option.

The way this is done in gcc is to pass -mthumb to the assembler with either
-Wa,-mthumb or -Xassembler -mthumb. This change adds support for these
options to clang. There is no assembler equivalent of -mno-thumb, -marm or
-mno-arm so we don't need to recognize these.

Ideally we would do all of the processing in
CollectArgsForIntegratedAssembler(). Unfortunately we need to change the
triple and at that point it is too late. Instead we look for the option
earlier in ComputeLLVMTriple().
    
Fixes PR34519
    
Differential Revision: https://reviews.llvm.org/D40127

llvm-svn: 318647
2017-11-20 13:43:55 +00:00
Kamil Rytarowski 86bff788eb Handle NetBSD specific indirection of libpthread functions
Summary:
Correct handling of three libpthread(3) functions on NetBSD:

 - pthread_mutex_lock(3),
 - pthread_mutex_unlock(3),
 - pthread_setcancelstate(3).

Code out of the libpthread(3) context uses the libc symbols:

 - __libc_mutex_lock,
 - __libc_mutex_unlock,
 - __libc_thr_setcancelstate.

The threading library (libpthread(3)) defines strong aliases:

 - __strong_alias(__libc_mutex_lock,pthread_mutex_lock)
 - __strong_alias(__libc_mutex_unlock,pthread_mutex_unlock)
 - __strong_alias(__libc_thr_setcancelstate,pthread_setcancelstate)

This caused that these functions were invisible to sanitizers on NetBSD.
Intercept the libc-specific ones and add them as NetBSD-specific aliases
for the common pthread(3) ones.

NetBSD needs to intercept both functions, as the regularly named ones
are used internally in libpthread(3).

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, dvyukov, vitalybuka

Reviewed By: dvyukov

Subscribers: llvm-commits, kubamracek, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D40241

llvm-svn: 318646
2017-11-20 12:21:11 +00:00
Gil Rapaport 8b9d1f3c5b [LV] Model masking in VPlan, introducing VPInstructions
This patch adds a new abstraction layer to VPlan and leverages it to model the planned
instructions that manipulate masks (AND, OR, NOT), introduced during predication.

The new VPValue and VPUser classes model how data flows into, through and out
of a VPlan, forming the vertices of a planned Def-Use graph. The new
VPInstruction class is a generic single-instruction Recipe that models a
planned instruction along with its opcode, operands and users. See
VectorizationPlan.rst for more details.

Differential Revision: https://reviews.llvm.org/D38676

llvm-svn: 318645
2017-11-20 12:01:47 +00:00
Ivan A. Kosarev fa03a6a034 [Driver] Add a cc1 flag for the new TBAA metadata format
This patch starts a series of changes to add support for the new
TBAA metadata format proposed in this llvm-dev thread:

http://lists.llvm.org/pipermail/llvm-dev/2017-November/118748.html

Differential Revision: https://reviews.llvm.org/D39955

llvm-svn: 318644
2017-11-20 11:16:16 +00:00
Diana Picus 3ac504035a [ARM GlobalISel] Add test for RSBri. NFC
Add instruction selector test for RSBri, which is derived from
AsI1_rbin_irs, and make sure it doesn't get mistaken for SUBri, which is
derived from the very similar AsI1_bin_irs pattern.

llvm-svn: 318643
2017-11-20 11:05:31 +00:00
Diana Picus 6db48f7d6b [ARM GlobalISel] Clean up binary operator tests. NFC
Remove some of the instruction selector tests for binary operators (and,
or, xor). These are all derived from the same kind of TableGen pattern,
AsI1_bin_irs, so there's no point in testing all of them.

llvm-svn: 318642
2017-11-20 10:35:35 +00:00
Mohammed Agabaria 115f68ea3e [LV][X86] Support of AVX2 Gathers code generation and update the LV with this
This patch depends on: https://reviews.llvm.org/D35348

Support of pattern selection of masked gathers of AVX2 (X86\AVX2 code gen)
Update LoopVectorize to generate gathers for AVX2 processors.

Reviewers: delena, zvi, RKSimon, craig.topper, aaboud, igorb

Reviewed By: delena, RKSimon

Differential Revision: https://reviews.llvm.org/D35772

llvm-svn: 318641
2017-11-20 08:18:12 +00:00
Craig Topper 198f7d78d3 [X86] Regenerate a test with broadcast comments. NFC
llvm-svn: 318640
2017-11-20 08:15:04 +00:00
Max Kazantsev 268467869b [IRCE] Smart range intersection
In rL316552, we ban intersection of unsigned latch range with signed range check and vice
versa, unless the entire range check iteration space is known positive. It was a correct
functional fix that saved us from dealing with ambiguous values, but it also appeared
to be a very restrictive limitation. In particular, in the following case:

  loop:
    %iv = phi i32 [ 0, %preheader ], [ %iv.next, %latch]
    %iv.offset = add i32 %iv, 10
    %rc = icmp slt i32 %iv.offset, %len
    br i1 %rc, label %latch, label %deopt

  latch:
    %iv.next = add i32 %iv, 11
    %cond = icmp i32 ult %iv.next, 100
    br it %cond, label %loop, label %exit

Here, the unsigned iteration range is `[0, 100)`, and the safe range for range
check is `[-10, %len - 10)`. For unsigned iteration spaces, we use unsigned
min/max functions for range intersection. Given this, we wanted to avoid dealing
with `-10` because it is interpreted as a very big unsigned value. Semantically, range
check's safe range goes through unsigned border, so in fact it is two disjoint
ranges in IV's iteration space. Intersection of such ranges is not trivial, so we prohibited
this case saying that we are not allowed to intersect such ranges.

What semantics of this safe range actually means is that we can start from `-10` and go
up increasing the `%iv` by one until we reach `%len - 10` (for simplicity let's assume that
`%len - 10`  is a reasonably big positive value).

In particular, this safe iteration space includes `0, 1, 2, ..., %len - 11`. So if we were able to return
safe iteration space `[0, %len - 10)`, we could safely intersect it with IV's iteration space. All
values in this range are non-negative, so using signed/unsigned min/max for them is unambiguous.

In this patch, we alter the algorithm of safe range calculation so that it returnes a subset of the
original safe space which is represented by one continuous range that does not go through wrap.
In order to reach this, we use modified SCEV substraction function. It can be imagined as a function
that substracts by `1` (or `-1`) as long as the further substraction does not cause a wrap in IV iteration
space. This allows us to perform IRCE in many situations when we deal with IV space and range check
of different types (in terms of signed/unsigned).

We apply this approach for both matching and not matching types of IV iteration space and the
range check. One implication of this is that now IRCE became smarter in detection of empty safe
ranges. For example, in this case:
  loop:
    %iv = phi i32 [ %begin, %preheader ], [ %iv.next, %latch]
    %iv.offset = sub i32 %iv, 10
    %rc = icmp ult i32 %iv.offset, %len
    br i1 %rc, label %latch, label %deopt

  latch:
    %iv.next = add i32 %iv, 11
    %cond = icmp i32 ult %iv.next, 100
    br it %cond, label %loop, label %exit

If `%len` was less than 10 but SCEV failed to trivially prove that `%begin - 10 >u %len- 10`,
we could end up executing entire loop in safe preloop while the main loop was still generated,
but never executed. Now, cutting the ranges so that if both `begin - 10` and `%len - 10` overflow,
we have a trivially empty range of `[0, 0)`. This in some cases prevents us from meaningless optimization.

Differential Revision: https://reviews.llvm.org/D39954

llvm-svn: 318639
2017-11-20 06:07:57 +00:00
Serguei Katkov 505359f705 [CGP] Fix the crash caused by enable of complex addr mode
We must collect all AddModes even if they are the same.
This is due to Original value is different but we need all original
values collected as they are used as anchors in common phi finding.

Reviewers: john.brawn, reames
Reviewed By: john.brawn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40166

llvm-svn: 318638
2017-11-20 05:42:36 +00:00
Peter Collingbourne 8e820552c3 COFF: Fix invalid comdat sections in test cases.
The comdat sections in these test cases do not comply with the COFF
specification, and link.exe rejects them. I plan to make a change to
how we handle comdat sections which would also cause us to reject them.

llvm-svn: 318637
2017-11-20 05:31:37 +00:00
Peter Collingbourne 5c7b467b6e COFF: Change SparseChunks to be of type std::vector<SectionChunk *>. NFC.
llvm-svn: 318636
2017-11-20 05:31:23 +00:00
Peter Collingbourne 38e3a1ea17 COFF: Remove unused fields. NFC.
llvm-svn: 318635
2017-11-20 05:31:09 +00:00
Craig Topper dcd69797a6 [X86] clzero check in getHostCPUFeatures should use getX86CpuIDAndInfo not getX86CpuIDAndInfoEx.
This leaf doesn't take an additional argument.

llvm-svn: 318634
2017-11-19 23:49:19 +00:00
Craig Topper 1af7e4424f [X86] Reorder and reformat the feature bit checks in getHostCPUFeatues to keep the bits in order per register and encourage future additions to be in order too.
llvm-svn: 318633
2017-11-19 23:30:22 +00:00
Philip Pfaffe 00fd43b327 Port ScopInfo to the isl cpp bindings
Summary:
Most changes are mechanical, but in one place I changed the program semantics
by fixing a likely bug:

In `Scop::hasFeasibleRuntimeContext()`, I'm now explicitely handling the
error-case. Before, when the call to `addNonEmptyDomainConstraints()`
returned a null set, this (probably) accidentally worked because
isl_bool_error converts to true. I'm checking for nullptr now.

Reviewers: grosser, Meinersbur, bollu

Reviewed By: Meinersbur

Subscribers: nemanjai, kbarton, pollydev, llvm-commits

Differential Revision: https://reviews.llvm.org/D39971

llvm-svn: 318632
2017-11-19 22:13:34 +00:00
Jan Kratochvil 0f45abdef7 Remove 2 unused methods DWARFDebugInfo::Find and their FindCallbackString
Differential revision: https://reviews.llvm.org/D40216

llvm-svn: 318631
2017-11-19 19:04:24 +00:00
Sanjay Patel c0218923e1 [x86] add sqrt tests for partially-inline-libcalls (PR31455)
llvm-svn: 318630
2017-11-19 17:31:37 +00:00
Sanjay Patel 9771a96f6e [LibCallSimplifier] allow splat vectors for pow(x, 0.5) -> sqrt() transforms
llvm-svn: 318629
2017-11-19 16:42:27 +00:00
Sanjay Patel fbd3e66b9a [LibCallSimplifier] partly fix pow(x, 0.5) -> sqrt() transforms
As the first test shows, we could transform an llvm intrinsic which never sets errno 
into a libcall which could set errno (even though it's marked readnone?), so that's 
not ideal.

It's possible that we can also transform a libcall which could set errno to an
intrinsic given the fast-math-flags constraint, but that's deferred to determine
exactly which set of FMF are needed.

Differential Revision: https://reviews.llvm.org/D40150

llvm-svn: 318628
2017-11-19 16:13:14 +00:00
Sanjay Patel eb731b09f3 [InstSimplify] fold and/or of fcmp ord/uno when operand is known nnan
The 'ord' and 'uno' predicates have a logic operation for NAN built into their definitions:

FCMP_ORD   =  7,  ///< 0 1 1 1    True if ordered (no nans)
FCMP_UNO   =  8,  ///< 1 0 0 0    True if unordered: isnan(X) | isnan(Y)

So we can simplify patterns like this:

(fcmp ord (known NNAN), X) && (fcmp ord X, Y) --> fcmp ord X, Y
(fcmp uno (known NNAN), X) || (fcmp uno X, Y) --> fcmp uno X, Y

It might be better to split this into (X uno 0) | (Y uno 0) as a canonicalization, but that
would be another patch.

Differential Revision: https://reviews.llvm.org/D40130 

llvm-svn: 318627
2017-11-19 15:34:27 +00:00
Jan Kratochvil d7ff94f035 Add comments to DWARFCompileUnit length fields/methods
Differential revision: https://reviews.llvm.org/D40211

llvm-svn: 318626
2017-11-19 14:35:07 +00:00
Eric Fiselier 577fa7f00f Attempt to fix template depth test failures on older Clang versions
llvm-svn: 318625
2017-11-19 09:46:34 +00:00
Craig Topper bece74c694 [X86] Add test cases for rndscaless/sd intrinsics.
Also fix the memop in the ins for these instructions. Not sure what effect this has.

llvm-svn: 318624
2017-11-19 06:24:26 +00:00
Craig Topper 512e9e7f3f [X86] Improve load folding of scalar rcp28 and rsqrt28 instructions using sse_load_f32/f64.
llvm-svn: 318623
2017-11-19 05:42:54 +00:00
Eric Fiselier afa6f83437 Fix min/max usage in variant
llvm-svn: 318622
2017-11-19 04:57:22 +00:00
Eric Fiselier 0ed525382f [libc++] Shrink variant's index type when possible
Summary:
Currently `std::variant` always uses an unsigned int to store the variant index. However this isn't nessesary and causes `std::variant` to be larger than it needs to be in most cases.

This patch changes the index type to be `unsigned char` when possible, and `unsigned short` or `unsigned int` otherwise, depending on the size (Although it's questionable if it's even possible to create a variant with 65535 elements.

Unfortunately this change is an ABI break, and as such is only enabled in ABI v2.

Reviewers: mpark

Reviewed By: mpark

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D40210

llvm-svn: 318621
2017-11-19 04:19:44 +00:00
Craig Topper fc1b8b12c7 [X86] Make sure 'knm' is accepted by -target-cpu
llvm-svn: 318620
2017-11-19 04:12:35 +00:00
Craig Topper e12ec3fc43 [X86] Make sure 'knm' and 'cannonlake' are accepted by builtin_cpu_is
llvm-svn: 318619
2017-11-19 04:12:33 +00:00
Eric Fiselier 518f24b5b9 Fix nodiscard test when modules are enabled
llvm-svn: 318618
2017-11-19 03:50:35 +00:00
Craig Topper 546cee4170 [X86] Add icelake CPU support for -march.
llvm-svn: 318617
2017-11-19 02:55:15 +00:00
Craig Topper 222c1725cd [X86] Set __corei7__ preprocessor defines for skylake server and cannonlake.
This is the resolution we came to in D38824.

llvm-svn: 318616
2017-11-19 02:55:14 +00:00
Alexei Starovoitov 9bd566f8c8 [bpf] remove unused variable
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 318615
2017-11-19 02:41:53 +00:00
Alexei Starovoitov 9a67245d88 [bpf] allow direct and indirect calls
kernel verifier is becoming smarter and soon will support
direct and indirect function calls.
Remove obsolete error from BPF backend.
Make call to use PCRel_4 fixup.
'bpf to bpf' calls are distinguished from 'bpf to kernel' calls
by insn->src_reg == BPF_PSEUDO_CALL == 1 which is used as relocation
indicator similar to ld_imm64->src_reg == BPF_PSEUDO_MAP_FD == 1
The actual 'call' instruction remains the same for both
'bpf to kernel' and 'bpf to bpf' calls.

Signed-off-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 318614
2017-11-19 01:35:00 +00:00
Craig Topper 9a94dfc457 [X86] Switch cannonlake to use the SkylakeServer scheduling model instead of Haswell.
Cannonlake comes after skylake and supports avx512 so this is probably a closer model for now.

llvm-svn: 318613
2017-11-19 01:25:30 +00:00
Craig Topper 81037f385e [X86] Add skeleton support for icelake CPU.
There are several patches out for review right now to implement Icelake features. This adds a CPU to collect them under.

llvm-svn: 318612
2017-11-19 01:12:00 +00:00
Craig Topper 17078ff0e0 [X86] Fix 80 column violation and remove trailing whitespace. NFC
llvm-svn: 318611
2017-11-19 01:11:58 +00:00
Craig Topper 436c9263fb [X86] Add cpu detection for cannonlake.
This uses the same encoding for cannonlake in the proposed gcc patches here. https://gcc.gnu.org/ml/gcc-patches/2017-11/msg00551.html

llvm-svn: 318610
2017-11-19 00:46:21 +00:00
Saleem Abdulrasool b3a66f7641 Driver: remove `SupportsObjCGC` (NFC)
This option is not used in the frontend.  Remove the method.

llvm-svn: 318609
2017-11-19 00:45:33 +00:00
Martell Malone 13c5d7379a [Driver] add initial support for alpine linux
set -pie as default for musl linux targets
add detection of alpine linux
append appropriate compile flags for alpine

Reviewers: rnk

Differential Revision: https://reviews.llvm.org/D39588

llvm-svn: 318608
2017-11-19 00:08:12 +00:00
Eric Fiselier c812560c14 [LIT] Fix testing out-of-tree Clang builds
Summary:
Currently, LIT configures the LLVM binary path before the Clang binary path. However this breaks testing out-of-tree Clang builds (where the LLVM binary path includes a copy of Clang).

This patch reverses the order of the paths when looking for Clang, putting the Clang binary directory first.

Reviewers: zturner, beanz, chapuni, modocache, EricWF

Reviewed By: EricWF

Subscribers: mgorny, cfe-commits, llvm-commits

Differential Revision: https://reviews.llvm.org/D40217

llvm-svn: 318607
2017-11-19 00:00:49 +00:00
Simon Pilgrim 72f40041f6 [MC][X86] Add test case from PR19251
llvm-svn: 318605
2017-11-18 23:23:25 +00:00
Simon Pilgrim 6960fe2e4e [MC][X86] Add teet case from PR32807
llvm-svn: 318603
2017-11-18 23:06:42 +00:00
Eric Fiselier 1ed231de44 Fix use of config.h in public headers.
The CodeGenCoverage.h header is installed, but it references
the build-only header "llvm/Config/config.h". This breaks use
of the CodeGenCoverage.h header once it is installed, because config.h isn't
available.

This patch fixes the error by moving the config.h include from
the CodeGenCoverage.h header (where it's not needed), to the
CodeGenCoverage.cpp source file.

llvm-svn: 318602
2017-11-18 22:42:26 +00:00
Jonas Hahnfeld 87d4426988 [OpenMP] Show error if VLAs are not supported
Some target devices (e.g. Nvidia GPUs) don't support dynamic stack
allocation and hence no VLAs. Print errors with description instead
of failing in the backend or generating code that doesn't work.

This patch handles explicit uses of VLAs (local variable in target
or declare target region) or implicitly generated (private) VLAs
for reductions on VLAs or on array sections with non-constant size.

Differential Revision: https://reviews.llvm.org/D39505

llvm-svn: 318601
2017-11-18 21:00:46 +00:00
Jonas Toth 9b1dc4c275 [clang-tidy] Add new hicpp-multiway-paths-covered check for missing branches
Summary:
This check searches for missing `else` branches in `if-else if`-chains and
missing `default` labels in `switch` statements, that use integers as condition.

It is very similar to -Wswitch, but concentrates on integers only, since enums are
already covered.

The option to warn for missing `else` branches is deactivated by default, since it is
very noise on larger code bases.

Running it on LLVM:
{F5354858} for default configuration
{F5354866} just for llvm/lib/Analysis/ScalarEvolution.cpp, the else-path checker is very noisy!

Reviewers: alexfh, aaron.ballman, hokein

Reviewed By: aaron.ballman

Subscribers: lebedev.ri, Eugene.Zelenko, cfe-commits, mgorny, JDevlieghere, xazax.hun

Tags: #clang-tools-extra

Differential Revision: https://reviews.llvm.org/D37808

llvm-svn: 318600
2017-11-18 19:48:33 +00:00
Simon Pilgrim 41fc45c4e6 [X86][AVX512VL] Add AVX512VL tests to the vselect packss tests.
PR34553 has gone, adding tests to ensure it doesn't come back.

vselect_packss_v16i64 still has some awful codegen on AVX512 targets....

llvm-svn: 318599
2017-11-18 19:47:59 +00:00