Commit Graph

14 Commits

Author SHA1 Message Date
Rafael Espindola f351292141 Remove redundant argument.
llvm-svn: 306189
2017-06-24 00:26:57 +00:00
Rafael Espindola 801b42de31 ARM: move some logic from processFixupValue to applyFixup.
processFixupValue is called on every relaxation iteration. applyFixup
is only called once at the very end. applyFixup is then the correct
place to do last minute changes and value checks.

While here, do proper range checks again for fixup_arm_thumb_bl. We
used to do it, but dropped because of thumb2. We now do it again, but
use the thumb2 range.

llvm-svn: 306177
2017-06-23 22:52:36 +00:00
Rafael Espindola 88d9e37ec8 Use a MutableArrayRef. NFC.
llvm-svn: 305968
2017-06-21 23:06:53 +00:00
Chandler Carruth 6bda14b313 Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.

I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.

This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.

Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).

llvm-svn: 304787
2017-06-06 11:49:48 +00:00
Matthias Braun 5e394c3d6f TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFC
TargetPassConfig is not useful for targets that do not use the CodeGen
library, so we may just as well store a pointer to an
LLVMTargetMachine instead of just to a TargetMachine.

While at it, also change the constructor to take a reference instead of a
pointer as the TM must not be nullptr.

llvm-svn: 304247
2017-05-30 21:36:41 +00:00
Konstantin Zhuravlyov dc77b2e960 Distinguish between code pointer size and DataLayout::getPointerSize() in DWARF info generation
llvm-svn: 300463
2017-04-17 17:41:25 +00:00
Alex Bradbury 866113c2ea Add MCContext argument to MCAsmBackend::applyFixup for error reporting
A number of backends (AArch64, MIPS, ARM) have been using
MCContext::reportError to report issues such as out-of-range fixup values in
their TgtAsmBackend. This is great, but because MCContext couldn't easily be
threaded through to the adjustFixupValue helper function from its usual
callsite (applyFixup), these backends ended up adding an MCContext* argument
and adding another call to applyFixup to processFixupValue. Adding an
MCContext parameter to applyFixup makes this unnecessary, and even better -
applyFixup can take a reference to MCContext rather than a potentially null
pointer.

Differential Revision: https://reviews.llvm.org/D30264

llvm-svn: 299529
2017-04-05 10:16:14 +00:00
Alex Bradbury e4f731b813 [RISCV] Fix RV32 datalayout string and ensure initAsmInfo is called
llvm-svn: 295028
2017-02-14 05:20:20 +00:00
Alex Bradbury 6be16fbfb8 [RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr
llvm-svn: 295027
2017-02-14 05:17:23 +00:00
Alex Bradbury d36e04cb6c [RISCV] Fix unused variable in RISCVMCTargetDesc. NFC
Also, for better uniformity use TargetRegistry::RegisterMCAsmInfo rather than 
RegisterMCAsmInfoFn. Again, no functional change.

llvm-svn: 295026
2017-02-14 05:15:24 +00:00
Aaron Ballman 3ac3a7efff Removing a switch statement that contains a default label, but no case labels. Silences an MSVC warning; NFC.
llvm-svn: 285806
2016-11-02 13:58:57 +00:00
Alex Bradbury 6b2cca7f8f [RISCV] Add bare-bones RISC-V MCTargetDesc
This is enough to compile and link but doesn't yet do anything particularly 
useful. Once an ASM parser and printer are added in the next two patches, the 
whole thing can be usefully tested.

Differential Revision: https://reviews.llvm.org/D23562

llvm-svn: 285770
2016-11-01 23:47:30 +00:00
Alex Bradbury 24d9b13b36 [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td
For now, only add instruction definitions for basic ALU operations. Our 
initial target is a working MC layer rather than codegen, so appropriate 
SelectionDAG patterns will come later.

Differential Revision: https://reviews.llvm.org/D23561

llvm-svn: 285769
2016-11-01 23:40:28 +00:00
Alex Bradbury b2e5472d85 [RISCV] Add stub backend
This contains just enough for lib/Target/RISCV to compile. Notably a basic 
RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc 
-march=riscv32 myinput.ll and will find it fails due to the lack of 
MCAsmInfo.

See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for 
further discussion

Differential Revision: https://reviews.llvm.org/D23560

llvm-svn: 285712
2016-11-01 17:27:54 +00:00