Commit Graph

387 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 8c139a5125 Clear kill flags before propagating a copy.
The live range of the source register may be extended when a redundant
copy is eliminated. Make sure any kill flags between the two copies are
cleared.

This fixes PR11765.

llvm-svn: 149069
2012-01-26 17:52:15 +00:00
Jakob Stoklund Olesen 374ed322f2 Add a new kind of MachineOperand: MO_RegisterMask.
Register masks will be used as a compact representation of large clobber
lists.  Currently, an x86 call instruction has some 40 operands
representing call-clobbered registers.  That's more than 1kB of useless
operands per call site.

A register mask operand references a bit mask of call-preserved
registers, everything else is clobbered.  The bit mask will typically
come from TargetRegisterInfo::getCallPreservedMask().

By abandoning ImplicitDefs for call-clobbered registers, it also becomes
possible to share call instruction descriptions between calling
conventions, and we can get rid of the WINCALL* instructions.

This patch introduces the new operand kind.  Future patches will add
RegMask support to target-independent passes before finally the fixed
clobber lists can be removed from call instruction descriptions.

llvm-svn: 148250
2012-01-16 19:22:00 +00:00
Chandler Carruth f3e8502cc1 Add 'llvm_unreachable' to passify GCC's understanding of the constraints
of several newly un-defaulted switches. This also helps optimizers
(including LLVM's) recognize that every case is covered, and we should
assume as much.

llvm-svn: 147861
2012-01-10 18:08:01 +00:00
David Blaikie edbb58c577 Remove unnecessary default cases in switches that cover all enum values.
llvm-svn: 147855
2012-01-10 16:47:17 +00:00
Evan Cheng 7fae11b231 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
2011-12-14 02:11:42 +00:00
Evan Cheng cdf89fdeaf Make MachineInstr instruction property queries more flexible. This change all
clients to decide whether to look inside bundled instructions and whether
the query should return true if any / all bundled instructions have the
queried property.

llvm-svn: 146168
2011-12-08 19:23:10 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen 6ad6848522 Add missing check.
llvm-svn: 146004
2011-12-07 01:08:22 +00:00
Jakob Stoklund Olesen b0d91abec0 Add MachineOperand IsInternalRead flag.
This flag is used when bundling machine instructions.  It indicates
whether the operand reads a value defined inside or outside its bundle.

llvm-svn: 145997
2011-12-07 00:22:07 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
2011-12-06 22:12:01 +00:00
Pete Cooper 82cd9e81fc Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100
2011-11-08 18:42:53 +00:00
Pete Cooper 65ba66c660 Reverted r143600 - selector reference change
llvm-svn: 143646
2011-11-03 20:47:50 +00:00
Pete Cooper e6173d81ae Treat objc selector reference globals as invariant so that MachineLICM can hoist them out of loops. Fixes <rdar://problem/6027699>
llvm-svn: 143600
2011-11-03 00:56:36 +00:00
Nick Lewycky 8488225984 Add missing braces to pacify GCC's -Wparentheses.
llvm-svn: 141842
2011-10-13 00:54:59 +00:00
Jakob Stoklund Olesen 35b362fab2 Add MachineInstr::getRegClassConstraint().
Most instructions have some requirements for their register operands.
Usually, this is expressed as register class constraints in the
MCInstrDesc, but for inline assembly the constraints are encoded in the
flag words.

llvm-svn: 141835
2011-10-12 23:37:36 +00:00
Jakob Stoklund Olesen 1e73716eae Extract a method for finding the inline asm flag operand.
llvm-svn: 141834
2011-10-12 23:37:33 +00:00
Jakob Stoklund Olesen 24abd9d9b6 Encode register class constreaints in inline asm instructions.
The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change during
coalescing, and the original constraint is lost.

Encode the original register class as part of the flag word for each
inline asm operand.  This makes it possible to recover the actual
constraint required by inline asm, just like we can for normal
instructions.

llvm-svn: 141833
2011-10-12 23:37:29 +00:00
Jakob Stoklund Olesen 463b05a2d0 Remove NumImplicitOps which is now unused.
llvm-svn: 140767
2011-09-29 01:47:36 +00:00
Jakob Stoklund Olesen 2318d1e0e9 Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.
The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.

This also fixes a bug when adding operands after an implicit operand has
been added manually.  The NumImplicitOps count wasn't kept up to date.

MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added.  It is possible to change an MI opcode and add additional
explicit operands.  They will be inserted before any existing implicit
operands.

The only exception is inline asm instructions where operands are never
reordered.  This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.

llvm-svn: 140744
2011-09-29 00:40:51 +00:00
Jim Grosbach ed16ec4248 Thumb2 parsing and encoding for IT blocks.
llvm-svn: 138773
2011-08-29 22:24:09 +00:00
Jim Grosbach dee9e8a37c Tidy up. Trailing whitespace.
llvm-svn: 138437
2011-08-24 16:44:17 +00:00
Jakob Stoklund Olesen 9eb77bf615 Don't treat a partial <def,undef> operand as a read.
Normally, a partial register def is treated as reading the
super-register unless it also defines the full register like this:

  %vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def>

This patch also uses the <undef> flag on partial defs to recognize
non-reading operands:

  %vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit

This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses
would treat a coalesced copy as still reading the register, extending
the live range artificially.

My test case only works when I disable DCE so a dead copy is left for
RegisterCoalescer, so I am not including it.

<rdar://problem/9967101>

llvm-svn: 138018
2011-08-19 00:30:17 +00:00
Devang Patel d61b1d505c Print DBG_VALUE variable's location info as a comment.
llvm-svn: 136916
2011-08-04 20:44:26 +00:00
Devang Patel bf8cc60d1b If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example,
DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 

llvm-svn: 134620
2011-07-07 17:45:33 +00:00
Jakob Stoklund Olesen 25a404eb81 Include a source location when complaining about bad inline assembly.
Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

llvm-svn: 134307
2011-07-02 03:53:34 +00:00
Cameron Zwarich 7da0f9a58e Take a stab at fixing the llvm-x86_64-linux-checks failure.
llvm-svn: 134287
2011-07-01 23:45:21 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Jakob Stoklund Olesen 537a302d1a Distinguish early clobber output operands from clobbered registers.
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

  asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

  asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

llvm-svn: 133902
2011-06-27 04:08:33 +00:00
Jakob Stoklund Olesen 6b356b18b4 Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:

  INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>

llvm-svn: 133901
2011-06-27 04:08:29 +00:00
Devang Patel f071d72c44 Handle debug info for i128 constants.
llvm-svn: 133821
2011-06-24 20:46:11 +00:00
Evan Cheng cfdf33904b Re-commit 131172 with fix. MachineInstr identity checks should check dead
markers. In some cases a register def is dead on one path, but not on
another.

This is passing Clang self-hosting.

llvm-svn: 131214
2011-05-12 00:56:58 +00:00
Jakob Stoklund Olesen 89bd2ae517 Remove an assertion to fix PR9872.
It can happen that a live debug variable is the last use of a sub-register, and
the register allocator will pick a larger register class for the virtual
register.  If the allocated register doesn't support the sub-register index,
just use %noreg for the debug variables instead of asserting.

In PR9872, a debug variable ends up in the sub_8bit_hi part of a GR32_ABCD
register. The register is split and one part is inflated to GR32 and assigned
%ESI because there are no more normal uses of sub_8bit_hi.

Since %ESI doesn't have that sub-register, substPhysReg asserted. Now it will
simply insert a %noreg instead, and the debug variable will be marked
unavailable in that range.

We don't currently have a way of saying: !"value" is in bits 8-15 of %ESI, I
don't know if DWARF even supports that.

llvm-svn: 131073
2011-05-08 19:21:08 +00:00
Bill Wendling 9f638ab181 Print out the 'nontemporal' info on a store.
llvm-svn: 130562
2011-04-29 23:45:22 +00:00
Jakob Stoklund Olesen 76ad3debab Ensure all defs referring to a virtual register are marked dead by addRegisterDead().
There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.

llvm-svn: 128888
2011-04-05 16:53:50 +00:00
Anton Korobeynikov 65cff414b6 Add FrameSetup MI flags
llvm-svn: 127098
2011-03-05 18:43:04 +00:00
Jakob Stoklund Olesen 2fb5b31578 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155
2011-01-10 02:58:51 +00:00
Jakob Stoklund Olesen 1331a15b0c Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.
Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

llvm-svn: 123107
2011-01-09 03:05:53 +00:00
Evan Cheng 6eb516dbea Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.

llvm-svn: 123044
2011-01-07 23:50:32 +00:00
Evan Cheng 0638c20e7c DBG_VALUE does not have any side effects; it also makes no sense to mark it cheap as a copy.
llvm-svn: 123031
2011-01-07 21:08:26 +00:00
Evan Cheng 21eedfb5a2 Unbreak build.
llvm-svn: 117155
2010-10-22 21:49:09 +00:00
Dan Gohman a94cc6dfe8 Make CodeGen TBAA-aware.
llvm-svn: 116890
2010-10-20 00:31:05 +00:00
Jakob Stoklund Olesen a4941690cc Shrink MachineOperand from 40 to 32 bytes on 64-bit hosts.
Pull an unsigned out of the Contents union such that it has the same size as two
pointers and no padding.

Arrange members such that the Contents union and all pointers can be 8-byte
aligned without padding.

This speeds up code generation by 0.8% on a 64-bit host. 32-bit hosts should be
unaffected.

llvm-svn: 116857
2010-10-19 20:56:32 +00:00
Chris Lattner 886250c8f0 convert a couple more places to use the new getStore()
llvm-svn: 114463
2010-09-21 18:51:21 +00:00
Chris Lattner 50287ea65a add some accessors
llvm-svn: 114409
2010-09-21 06:43:24 +00:00
Chris Lattner 82fd06d3ce it's more elegant to put the "getConstantPool" and
"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.

llvm-svn: 114406
2010-09-21 06:22:23 +00:00
Chris Lattner de93bb065d add some helpful accessors.
llvm-svn: 114400
2010-09-21 05:39:30 +00:00
Chris Lattner 00ca0b8e98 start pushing MachinePointerInfo out through the MachineMemOperand interface
to the MachineFunction construction methods.

llvm-svn: 114390
2010-09-21 04:32:08 +00:00
Chris Lattner 187f653418 refactor the Value*/offset pair from MachineMemOperand out to a new
MachinePointerInfo struct, no functionality change.

This also adds an assert to MachineMemOperand::MachineMemOperand
that verifies that the Value* is either null or is an IR pointer type.

llvm-svn: 114389
2010-09-21 04:23:39 +00:00
Oscar Fuentes 40b31ad3ee Prefix `next' iterator operation with `llvm::'.
Fixes potential ambiguity problems on VS 2010.

Patch by nobled!

llvm-svn: 110029
2010-08-02 06:00:15 +00:00
Jakob Stoklund Olesen 0ff2c110ad Print out the regclass of any virtual registers used by a machine instruction.
llvm-svn: 109608
2010-07-28 18:35:46 +00:00