Commit Graph

3512 Commits

Author SHA1 Message Date
Kit Barton 6646033e6e This patch adds support for the vector quadword add/sub instructions introduced
in POWER8:

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
In addition to adding the instructions themselves, it also adds support for the
v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and
IntrinsicEmitter.cpp).

http://reviews.llvm.org/D9081

llvm-svn: 238144
2015-05-25 15:49:26 +00:00
Craig Topper be91e627d9 [TableGen] Remove ListInit::size() in favor of getSize() which does the same thing and is already used in most places. NFC.
llvm-svn: 237341
2015-05-14 05:53:56 +00:00
Craig Topper ec9072d661 [TableGen] Replace some calls to ListInit::getSize() with ListInit::empty() if it was just comparing to 0. NFC.
llvm-svn: 237340
2015-05-14 05:53:53 +00:00
Jim Grosbach e9119e41ef MC: Modernize MCOperand API naming. NFC.
MCOperand::Create*() methods renamed to MCOperand::create*().

llvm-svn: 237275
2015-05-13 18:37:00 +00:00
Michael Kuperstein c3434b390d Reverting r237234, "Use std::bitset for SubtargetFeatures"
The buildbots are still not satisfied.
MIPS and ARM are failing (even though at least MIPS was expected to pass).

llvm-svn: 237245
2015-05-13 10:28:46 +00:00
Michael Kuperstein aba4a34ef2 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first two times this was committed (r229831, r233055), it caused several buildbot failures. 
At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed.

llvm-svn: 237234
2015-05-13 08:27:08 +00:00
James Y Knight e452e27129 Fix tablegen's PrintFatalError function to run registered file
cleanups.

Also, change code in tablegen which printed a message and then called
"exit(1)" to use PrintFatalError, instead.

This fixes instances where an empty output file was left behind after
a failed tablegen invocation, which would confuse subsequent ninja
runs into not attempting to rebuild.

Differential Revision: http://reviews.llvm.org/D9608

llvm-svn: 237058
2015-05-11 22:17:13 +00:00
Craig Topper ba6057de71 [TableGen] Don't leak Expanders and Operators in SetTheory.
llvm-svn: 235697
2015-04-24 06:49:44 +00:00
Craig Topper 1bf3d1f5dd [TableGen] Use 'isa' to identify UnsetInits rather than comparing with the singleton object created by UnsetInit::get(). Makes it more consistent with the other types.
llvm-svn: 235465
2015-04-22 02:09:45 +00:00
Elena Demikhovsky 0e6d6d54ce AVX-512: Added VPMOVx2M instructions for SKX,
fixed encoding of VPMOVM2x.

llvm-svn: 235385
2015-04-21 14:38:31 +00:00
Elena Demikhovsky 431b81e41f AVX-512: Added VPTESTM and VPTESTNM instructions for SKX
llvm-svn: 235383
2015-04-21 13:13:46 +00:00
Kit Barton f4669f5905 Add support for v1i128 type.
The v1i128 type is needed for the quadword add/substract instructions introduced
in POWER8. Futhermore, the PowerPC ABI specifies that parameters of type v1i128
are to be passed in a single vector register, while parameters of type i128 are
passed in pairs of GPRs. Thus, it is necessary to be able to differentiate
between v1i128 and i128 in LLVM.

http://reviews.llvm.org/D8564

llvm-svn: 235198
2015-04-17 16:11:05 +00:00
Richard Trieu 6b1aa5f5e1 Change range-based for-loops to be -Wrange-loop-analysis clean.
No functionality change.

llvm-svn: 234963
2015-04-15 01:21:15 +00:00
Alexander Kornienko f817c1cb9a Use 'override/final' instead of 'virtual' for overridden methods
The patch is generated using clang-tidy misc-use-override check.

This command was used:

  tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \
    -checks='-*,misc-use-override' -header-filter='llvm|clang' \
    -j=32 -fix -format

http://reviews.llvm.org/D8925

llvm-svn: 234679
2015-04-11 02:11:45 +00:00
Craig Topper 8b88cc284f Use SmallVector instead of std::vector for uniquing X86 disassembler operand sets. The number of operands is a small fixed size.
llvm-svn: 234465
2015-04-09 04:08:48 +00:00
Craig Topper 34136874fd Simplify some printing code by combining new lines onto previous strings. Don't work so hard not to print a comma on the last entry of an array.
llvm-svn: 234464
2015-04-09 04:08:46 +00:00
Craig Topper d434e39557 Don't convert enum to strings just to put them in the uniquing map. Use the enum directly. Only convert to a string for printing.
llvm-svn: 234463
2015-04-09 04:08:42 +00:00
Craig Topper 08f4bd2847 Revert r234389. It really was needed but really should have been cstring instead of string.h
llvm-svn: 234390
2015-04-08 06:03:17 +00:00
Craig Topper 9bfac7b2e3 Remove unnecessary include. NFC
llvm-svn: 234389
2015-04-08 05:56:30 +00:00
Toma Tabacu 3d5ce49ce5 [TableGen] Prevent invalid code generation when emitting AssemblerPredicate conditions.
Summary:
The loop which emits AssemblerPredicate conditions also links them together by emitting a '&&'.
If the 1st predicate is not an AssemblerPredicate, while the 2nd one is, nothing gets emitted for the 1st one, but we still emit the '&&' because of the 2nd predicate.
This generated code looks like "( && Cond2)" and is invalid.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D8294

llvm-svn: 234312
2015-04-07 12:10:11 +00:00
Matthias Braun d85d09bfb5 TableGen: Generate more const goodness
llvm-svn: 233857
2015-04-01 22:09:55 +00:00
Matthias Braun d5fa8fb106 Fix AllocationPriority not getting set for derived register classes.
llvm-svn: 233752
2015-03-31 20:52:25 +00:00
Matthias Braun a354cdd0c5 RegAllocGreedy: Allow target to specify register class ordering.
Specify an allocation order with a register class. This is used by register
allocators with a greedy heuristic. This is usefull as it is sometimes
beneficial to color more constrained classes first.

Differential Revision: http://reviews.llvm.org/D8626

llvm-svn: 233743
2015-03-31 19:57:53 +00:00
Akira Hatanaka b46d0234a6 [MCInstPrinter] Enable MCInstPrinter to change its behavior based on the
per-function subtarget.

Currently, code-gen passes the default or generic subtarget to the constructors
of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which
enables some targets (AArch64, ARM, and X86) to change their instprinter's
behavior based on the subtarget feature bits. Since the backend can now use
different subtargets for each function, instprinter has to be changed to use the
per-function subtarget rather than the default subtarget.

This patch takes the first step towards enabling instprinter to change its
behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to
AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the
various print methods table-gen auto-generates. 

I will follow up with changes to instprinters of AArch64, ARM, and X86.

llvm-svn: 233411
2015-03-27 20:36:02 +00:00
Michael Kuperstein 29704e7fb4 Revert "Use std::bitset for SubtargetFeatures"
This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time.

llvm-svn: 233068
2015-03-24 12:56:59 +00:00
Michael Kuperstein 774b441b5e Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first time this was committed (r229831), it caused several buildbot failures. 
At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed.

Differential Revision: http://reviews.llvm.org/D8542

llvm-svn: 233055
2015-03-24 09:17:25 +00:00
Benjamin Kramer b85d3756a6 Another set of missing raw_ostream.h. Still no functional change.
llvm-svn: 232993
2015-03-23 18:45:56 +00:00
Craig Topper 3a8eb896c9 [Tablegen] Attempt to add support for patterns containing nodes with multiple results.
This is needed for AVX512 masked scatter/gather support.

The R600 change is necessary to remove a hack that was working around the lack of multiple results.

llvm-svn: 232798
2015-03-20 05:09:06 +00:00
Matthias Braun a25e13aaf1 Do not track subregister liveness when it brings no benefits
Some subregisters are only to indicate different access sizes, while not
providing any way to actually divide the register up into multiple
disjunct parts. Avoid tracking subregister liveness in these cases as it
is not beneficial.

Differential Revision: http://reviews.llvm.org/D8429

llvm-svn: 232695
2015-03-19 00:21:58 +00:00
Matthias Braun 3b36533112 TableGen: Fix register class lane masks being too conservative.
When calculating the lanemask of a register class we have to include the
masks of subregisters supported by any of the class members, not just
the ones supported by all class members.

This fixes problems when coalescing towards a subclass with additional
subregisters available.

The attached testcase works fine as is, but does crash if you enable
subregister liveness on x86 without this change applied.

llvm-svn: 232652
2015-03-18 17:56:09 +00:00
Yaron Keren 92e1b62d45 Remove many superfluous SmallString::str() calls.
Now that SmallString is a first-class citizen, most SmallString::str()
calls are not required. This patch removes a whole bunch of them, yet
there are lots more.

There are two use cases where str() is really needed:
1) To use one of StringRef member functions which is not available in
SmallString.
2) To convert to std::string, as StringRef implicitly converts while 
SmallString do not. We may wish to change this, but it may introduce
ambiguity.

llvm-svn: 232622
2015-03-18 10:17:07 +00:00
Eric Christopher 44fd498a04 Use the variable names from the TargetInstrInfo source when we
reference them in the generated files. A few characters aren't huge
here and CFSetupOpcode is much more readable than S0.

llvm-svn: 232132
2015-03-13 01:26:39 +00:00
Eric Christopher 69c0a7c981 Add a return after the llvm namespace code for a little extra
readability in generated files.

llvm-svn: 232131
2015-03-13 01:10:08 +00:00
Eric Christopher 4320495319 Have getRegPressureSetLimit take a MachineFunction so that a
we can inspect the subtarget and function when computing values.

llvm-svn: 231951
2015-03-11 18:34:58 +00:00
Yaron Keren 09fb7c6e7a Teach raw_ostream to accept SmallString.
Saves adding .str() call to any raw_ostream << SmallString usage
and a small step towards making .str() consistent in the ADTs by
removing one of the SmallString::str() use cases, discussion at

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141013/240026.html

I'll update the Phabricator patch http://reviews.llvm.org/D6372
for review of the Twine SmallString support, it's more complex
than this one.

llvm-svn: 231763
2015-03-10 07:33:23 +00:00
Craig Topper 7bbd37b277 Improve and simplify EnforceSmallerThan for vector types.
Explicitly compare the size of the scalar types and the whole vector size rather than just comparing enum encodings.

llvm-svn: 231746
2015-03-10 03:25:07 +00:00
Craig Topper 0d1fb90e3c Remove extra indentation of entire function body. NFC.
llvm-svn: 231745
2015-03-10 03:25:04 +00:00
Reid Kleckner 294fa7aa9d TableGen: Use 'enum : uint64_t' for feature flags to fix -Wmicrosoft
clang-cl would warn that this value is not representable in 'int':
  enum { FeatureX = 1ULL << 31 };
All MS enums are 'ints' unless otherwise specified, so we have to use an
explicit type.  The AMDGPU target just hit 32 features, triggering this
warning.

Now that we have C++11 strong enum types, we can also eliminate the
'const uint64_t' codepath from tablegen and just use 'enum : uint64_t'.

llvm-svn: 231697
2015-03-09 20:23:14 +00:00
Tom Stellard 5698d63348 TableGen: Initialize ErrorInfo to ~0ULL in the MatchInstructionImpl
This is what all the targets check for and is consistent with the
initialized value of MissingFeatures, which is sometimes assinged
to ErrorInfo.

llvm-svn: 231397
2015-03-05 19:46:55 +00:00
Craig Topper 35b3dbc4a3 Revert "[TableGen] Implement at least some support for multiple explicit results in an instruction pattern. No functional change to existing patterns."
This is failing on several build bots.

llvm-svn: 231358
2015-03-05 07:17:52 +00:00
Craig Topper 5edbf1ccaf [TableGen] Implement at least some support for multiple explicit results in an instruction pattern. No functional change to existing patterns.
This should help with the AVX512 masked gather changes Elena is working on. This patch is derived from some of the changes Elena made to tablegen, but modified by me to support arbitrary number of results.

llvm-svn: 231357
2015-03-05 07:11:36 +00:00
Craig Topper 0be3458006 [TableGen] Add support constraining a vector type in a pattern to have a specific element type and for constraining a vector type to have the same number of elements as another vector type. This is useful for AVX512 mask operations so we relate the mask type to the type of the other arguments.
llvm-svn: 231356
2015-03-05 07:11:34 +00:00
David Blaikie eb6c31f900 Add a FIXME for PR22796, broken ordering of ClassInfo in TableGen
As discussed (at length) in code review of r222935, with Duncan.

llvm-svn: 231282
2015-03-04 19:56:44 +00:00
Craig Topper 483a3000f5 [Tablegen] Use correct result number variables with the pattern nodes they go with when handling SDTCisSameAs. No functional change as they are always both 0 unless you try to define a multi result type profile that uses SDTCisSame on one of the other results.
llvm-svn: 231226
2015-03-04 09:04:54 +00:00
David Blaikie 7f1e0565b3 Revert "Remove the explicit SDNodeIterator::operator= in favor of the implicit default"
Accidentally committed a few more of these cleanup changes than
intended. Still breaking these out & tidying them up.

This reverts commit r231135.

llvm-svn: 231136
2015-03-03 21:18:16 +00:00
David Blaikie bb8da4c08f Remove the explicit SDNodeIterator::operator= in favor of the implicit default
There doesn't seem to be any need to assert that iterator assignment is
between iterators over the same node - if you want to reuse an iterator
variable to iterate another node, that's perfectly acceptable. Just
don't mix comparisons between iterators into disjoint sequences, as
usual.

llvm-svn: 231135
2015-03-03 21:17:08 +00:00
Nick Lewycky b1de8c2b73 Switch up whitespace with better whitespace.
llvm-svn: 231059
2015-03-03 07:59:45 +00:00
Nick Lewycky fe9cee7b0a Revert the non-cleanup part of r230769 because it introduced a non-determinism found only in the names of symbols.
llvm-svn: 231058
2015-03-03 07:57:45 +00:00
Benjamin Kramer e1e33139c5 TblGen: Remove copy of SmallVector::operator==. NFC intended.
llvm-svn: 230964
2015-03-02 15:24:30 +00:00
Benjamin Kramer 0a446fd56c Add missing includes. make_unique proliferated everywhere.
llvm-svn: 230909
2015-03-01 21:28:53 +00:00