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32 Commits

Author SHA1 Message Date
Eli Friedman 6613efbd4e [ARM] Add missing Thumb2 assembler diagnostics. 
Mostly just adding checks for Thumb2 instructions which correspond to
ARM instructions which already had diagnostics. While I'm here, also fix
ARM-mode strd to check the input registers correctly.

Differential Revision: https://reviews.llvm.org/D48610

llvm-svn: 335909
 2018-06-28 19:53:12 +00:00
Saleem Abdulrasool e6e6d71477 ARM IAS: support GNU extension for ldrd, strd 
The GNU assembler has an extension that allows for the elision of the paired
register (dt2) for the LDRD and STRD mnemonics.  Add support for this in the
assembly parser.  Canonicalise the usage during the instruction parsing from
the specified version.

llvm-svn: 198915
 2014-01-10 04:38:35 +00:00
Tilmann Scheller 1aebfa0a9b ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands. 
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:

LDRD<c> <Rt>, <Rt2>, ...

(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)

If those two constraints are not met the result of executing the instruction will be unpredictable.

Constraint (b) was already enforced, this commit adds support for constraint (a).

Fixes rdar://14479793.

llvm-svn: 191520
 2013-09-27 13:28:17 +00:00
Mihai Popa c1d119ed6e It adds support for negative zero offsets for loads and stores. 
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.

llvm-svn: 183734
 2013-06-11 09:48:35 +00:00
Jim Grosbach 8648c10184 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

llvm-svn: 146921
 2011-12-19 23:06:24 +00:00
Jim Grosbach a2b8b60646 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Jim Grosbach 7db3bfbd45 ARM STRHT assembly parsing and encoding. 
llvm-svn: 137358
 2011-08-11 21:39:41 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach d0767f37c1 Add FIXME. 
llvm-svn: 137336
 2011-08-11 19:43:42 +00:00
Jim Grosbach 295788756d ARM STRB assembly parsing and encoding tests. 
llvm-svn: 137335
 2011-08-11 19:42:58 +00:00
Jim Grosbach 14a4164206 Fix a copy/paste error so that LDRB(register) actually gets tested. 
llvm-svn: 137333
 2011-08-11 19:34:23 +00:00
Jim Grosbach 06b7f0c901 ARM STR(register) assembly parsing and encoding tests. 
llvm-svn: 137332
 2011-08-11 19:26:17 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Jim Grosbach 94ba2cba6e ARM tests for LDRSHT assembly parsing and encoding. 
llvm-svn: 137274
 2011-08-10 23:18:30 +00:00
Jim Grosbach a6ab52bf9f ARM tests for LDRSH assembly parsing and encoding. 
llvm-svn: 137272
 2011-08-10 23:12:25 +00:00
Jim Grosbach 2953404723 ARM tests for LDRSBT assembly parsing and encoding. 
llvm-svn: 137271
 2011-08-10 23:08:56 +00:00
Jim Grosbach c11bbf3bda ARM tests for LDRSB assembly parsing and encoding. 
llvm-svn: 137270
 2011-08-10 23:06:44 +00:00
Jim Grosbach 35cdf36c32 Add FIXME. 
llvm-svn: 137265
 2011-08-10 22:56:43 +00:00
Jim Grosbach 5e0c9711f2 ARM tests for LDRHT assembly parsing and encoding. 
llvm-svn: 137263
 2011-08-10 22:55:38 +00:00
Jim Grosbach 7cd4253cc3 ARM tests for LDRH(register) assembly parsing and encoding. 
llvm-svn: 137261
 2011-08-10 22:45:42 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach ae1b002fa3 Add FIXME 
llvm-svn: 137258
 2011-08-10 22:20:38 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Jim Grosbach cab35c0836 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
 2011-08-08 23:28:47 +00:00
Jim Grosbach 5838c0c47e ARM parsing and encoding for LDRB instruction. 
llvm-svn: 137071
 2011-08-08 22:37:06 +00:00
Jim Grosbach f6dbc3a57c Add FIXME. 
llvm-svn: 137070
 2011-08-08 22:11:33 +00:00
Jim Grosbach 3d0b3a3a50 ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
 2011-08-05 22:03:36 +00:00
Jim Grosbach c320c85261 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
 2011-08-05 21:28:30 +00:00
Jim Grosbach 0f2dd284e9 Add ARM LDR parsing tests. 
llvm-svn: 136977
 2011-08-05 20:33:39 +00:00