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73 Commits

Author SHA1 Message Date
Evan Cheng 62d626ce86 Fix zero and sign extension instructions scheduling itineraries. 
llvm-svn: 114780
 2010-09-25 00:49:35 +00:00
Evan Cheng e37da03e60 More pseudo instruction scheduling itinerary fixes. 
llvm-svn: 114768
 2010-09-24 22:41:41 +00:00
Evan Cheng 1d35ad62cc Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 
llvm-svn: 114766
 2010-09-24 22:03:46 +00:00
Evan Cheng 367a5df8cf For each instruction itinerary class, specify the number of micro-ops each 
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513
 2010-09-09 18:18:55 +00:00
Evan Cheng 722cd122dc Fix LDM_RET schedule itinery. 
llvm-svn: 113435
 2010-09-08 22:57:08 +00:00
Anton Korobeynikov 7d62e33291 Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
 2010-04-18 20:31:01 +00:00
Anton Korobeynikov 090323aee5 Split A8/A9 itins - they already were too big. 
llvm-svn: 100672
 2010-04-07 18:22:11 +00:00
Anton Korobeynikov a248becd6c Fix itins for VABA 
llvm-svn: 100657
 2010-04-07 18:20:42 +00:00
Anton Korobeynikov 7d4fad5942 VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. 
llvm-svn: 100652
 2010-04-07 18:20:13 +00:00
Anton Korobeynikov 2063705d91 Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( 
llvm-svn: 100650
 2010-04-07 18:20:02 +00:00
Anton Korobeynikov 4c1da0f82a Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. 
llvm-svn: 100647
 2010-04-07 18:19:46 +00:00
Anton Korobeynikov baeb210be7 Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly. 
llvm-svn: 100646
 2010-04-07 18:19:40 +00:00
David Goodwin bea6848f9d Finish scheduling itineraries for NEON. 
llvm-svn: 82788
 2009-09-25 18:38:29 +00:00
David Goodwin bf97147a7e Make the end-of-itinerary mark explicit. Some cleanup. 
llvm-svn: 82709
 2009-09-24 20:22:50 +00:00
David Goodwin afcaf79603 Checkpoint NEON scheduling itineraries. 
llvm-svn: 82657
 2009-09-23 21:38:08 +00:00
David Goodwin 5090273367 Add Cortex-A8 VFP model. 
llvm-svn: 82483
 2009-09-21 20:52:17 +00:00
David Goodwin a7c2dfbca1 Update Cortex-A8 instruction itineraries for integer instructions. 
llvm-svn: 79436
 2009-08-19 18:00:44 +00:00
Evan Cheng 6ddd7bcdd1 Turn on if-conversion for thumb2. 
llvm-svn: 79084
 2009-08-15 07:59:10 +00:00
David Goodwin a9c2aad939 Finalize itineraries for cortex-a8 integer multiply 
llvm-svn: 78908
 2009-08-13 15:51:13 +00:00
David Goodwin fd5defed1d Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter. 
llvm-svn: 78736
 2009-08-11 22:38:43 +00:00
David Goodwin 62e053b790 Checkpoint scheduling itinerary changes. 
llvm-svn: 78564
 2009-08-10 15:56:13 +00:00
Evan Cheng 18e32946f8 Add fake v7 itineraries for now. 
llvm-svn: 76612
 2009-07-21 18:54:14 +00:00
Evan Cheng 4e712de541 Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. 
llvm-svn: 73747
 2009-06-19 01:51:50 +00:00