Commit Graph

408 Commits

Author SHA1 Message Date
Shoaib Meenai 8c023a9cd9 [ELF] Fix typo in comment. NFC
llvm-svn: 321022
2017-12-18 20:33:27 +00:00
Peter Smith 3c73a41128 [ELF] Optimize Arm PLT sequences
A more efficient PLT sequence can be used when the distance between the
.plt and the end of the .plt.got is less than 128 Megabytes, which is
frequently true. We fall back to the old sequence when the offset is larger
than 128 Megabytes. This gives us an alternative to forcing the longer
entries with --long-plt as we gracefully fall back to it as needed. 

See ELF for the ARM Architecture Appendix A for details of the PLT sequence.

Differential Revision: https://reviews.llvm.org/D41246

llvm-svn: 320987
2017-12-18 14:46:27 +00:00
Rafael Espindola 9c8d7f8dcc Return R_PLT_PC for R_PPC_PLTREL24.
The PPC port doesn't support PLT yet, but the architecture independent
code optimizes PLT access for non preemptible symbols, which is
exactly what returning R_PC was trying to implement.

llvm-svn: 320430
2017-12-11 22:40:18 +00:00
Tim Northover 8f1bc370e2 PPC32: Support R_PPC_PLTREL32 in static mode.
See https://reviews.llvm.org/D39226

Patch by vit9696 <vit9696@avp.su>

llvm-svn: 320286
2017-12-10 08:42:34 +00:00
Alexander Richardson 280252c6d1 [ELF][mips] Print the full file path for files with incompatible ISA
Summary:
I also changed the message to print both the ISA and the the architecture
name for incompatible files. Previously it would be quite hard to find the
actual path of the incompatible object files in projects that have many
object files with the same name in different directories.

Reviewers: atanasyan, ruiu

Reviewed By: atanasyan

Subscribers: emaste, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D40958

llvm-svn: 320056
2017-12-07 16:08:59 +00:00
Peter Smith 31dddc97ae [ELF][AArch64] Add support for AArch64 range thunks.
The AArch64 unconditional branch and branch and link instructions have a
maximum range of 128 Mib. This is usually enough for most programs but
there are cases when it isn't enough. This change adds support for range
extension thunks to AArch64. For pc-relative thunks we follow the small
code model and use ADRP, ADD, BR. This has a limit of 4 gigabytes.

Differential Revision: https://reviews.llvm.org/D39744

llvm-svn: 319307
2017-11-29 11:15:12 +00:00
Peter Smith 2809926c4d [ELF][ARM] Refine check for when undefined weak needs a Thunk
When an undefined weak reference has a PLT entry we must generate a range
extension thunk for any B or BL that can't reach the PLT entry.

This change explicitly looks for whether a PLT entry exists rather than
assuming that weak references never need PLT entries unless Config->Shared
is in operation. This covers the case where we are linking an executable
with dynamic linking, hence a PLT entry will be needed for undefined weak
references. This case comes up in real programs over 32 Mb in size as there
is a B to a weak reference __gmon__start__ in the Arm crti.o for glibc.

Differential Revision: https://reviews.llvm.org/D40248

llvm-svn: 319020
2017-11-27 11:49:18 +00:00
Simon Atanasyan 167306a56c [MIPS] Write PLT0 entry in case of linking N64 ABI code
llvm-svn: 318831
2017-11-22 12:34:29 +00:00
Simon Atanasyan cfa8aa7edb [MIPS] Set STO_MIPS_MICROMIPS flag and less-significant bit for microMIPS symbols
microMIPS symbols including microMIPS PLT records created for regular
symbols needs to be marked by STO_MIPS_MICROMIPS flag in a symbol table.
Additionally microMIPS entries in a dynamic symbol table should have
configured less-significant bit. That allows to escape teaching a
dynamic linker about microMIPS symbols.

llvm-svn: 318097
2017-11-13 22:40:36 +00:00
Simon Atanasyan 5a4e21364c [MIPS] Setup less-significant bit in the .got and .got.plt entries in case of microMIPS code
The less-significant bit signals about microMIPS code for jump/branch
instructions.

llvm-svn: 317741
2017-11-08 23:34:34 +00:00
Rui Ueyama 7957b08e87 Move MIPS-specific code from Symbols.cpp to MIPS.cpp.
We have a lot of "if (MIPS)" conditions in lld because the MIPS' ABI
is different at various places than other arch's ABIs at where it
don't have to be different, but we at least want to reduce MIPS-ness
from the regular classes.

llvm-svn: 317525
2017-11-07 00:04:22 +00:00
Peter Collingbourne e9a9e0a1e7 ELF: Merge DefinedRegular and Defined.
Now that DefinedRegular is the only remaining derived class of
Defined, we can merge the two classes.

Differential Revision: https://reviews.llvm.org/D39667

llvm-svn: 317448
2017-11-06 04:35:31 +00:00
Rui Ueyama f52496e1e0 Rename SymbolBody -> Symbol
Now that we have only SymbolBody as the symbol class. So, "SymbolBody"
is a bit strange name now. This is a mechanical change generated by

  perl -i -pe s/SymbolBody/Symbol/g $(git grep -l SymbolBody lld/ELF lld/COFF)

nd clang-format-diff.

Differential Revision: https://reviews.llvm.org/D39459

llvm-svn: 317370
2017-11-03 21:21:47 +00:00
Peter Smith 75030b6d56 [ELF] Introduce range extension thunks for ARM
This change adds initial support for range extension thunks. All thunks must
be created within the first pass so some corner cases are not supported. A
follow up patch will add support for multiple passes.

With this change the existing tests arm-branch-error.s and
arm-thumb-branch-error.s now no longer fail with an out of range branch.
These have been renamed and tests added for the range extension thunk.

Differential Revision: https://reviews.llvm.org/D34691

llvm-svn: 316752
2017-10-27 09:04:11 +00:00
Peter Smith f0c70f8d34 [ELF] Pre-create ThunkSections at Target specific intervals
When an OutputSection is larger than the branch range for a Target we
need to place thunks such that they are always in range of their caller,
and sufficiently spaced to maximise the number of callers that can use
the thunk. We use the simple heuristic of placing the
ThunkSection at intervals corresponding to a target specific branch range.
If the OutputSection is small we put the thunks at the end of the executable
sections.

Differential Revision: https://reviews.llvm.org/D34689

llvm-svn: 316751
2017-10-27 08:58:28 +00:00
Rui Ueyama ed55e6c64f Remove an unnecessary inheritance.
llvm-svn: 316716
2017-10-26 23:54:00 +00:00
Bob Haarman b8a59c8aa5 [lld] unified COFF and ELF error handling on new Common/ErrorHandler
Summary:
The COFF linker and the ELF linker have long had similar but separate
Error.h and Error.cpp files to implement error handling. This change
introduces new error handling code in Common/ErrorHandler.h, changes the
COFF and ELF linkers to use it, and removes the old, separate
implementations.

Reviewers: ruiu

Reviewed By: ruiu

Subscribers: smeenai, jyknight, emaste, sdardis, nemanjai, nhaehnle, mgorny, javed.absar, kbarton, fedor.sergeev, llvm-commits

Differential Revision: https://reviews.llvm.org/D39259

llvm-svn: 316624
2017-10-25 22:28:38 +00:00
Rui Ueyama f8f4620dc6 Move comment to the place where it makes more sense.
llvm-svn: 316491
2017-10-24 20:11:07 +00:00
Rui Ueyama 51f604ce66 Simplify.
llvm-svn: 316486
2017-10-24 19:40:03 +00:00
Konstantin Zhuravlyov b71d1b8a54 LLD/ELF/AMDGPU: Process AMDGPU-specific e_flags
Differential Revision: https://reviews.llvm.org/D39140

llvm-svn: 316483
2017-10-24 19:05:32 +00:00
Konstantin Zhuravlyov e7f1734f1a LLD/ELF: Allow targets to set e_flags
Differential Revision: https://reviews.llvm.org/D39139

llvm-svn: 316460
2017-10-24 17:01:40 +00:00
Rui Ueyama 8faafa4fb1 Add R_PPC_ADDR16_HI relocation support
The support of R_PPC_ADDR16_HI improves ld compatibility and makes
things on par with RuntimeDyldELF that already implements this
relocation.

Patch by vit9696.

llvm-svn: 316306
2017-10-22 23:33:49 +00:00
Tony Tye 394e1dde6e Add base relative relocation record that can be used for the following case (OpenCL example):
static __global int Var = 0; 
__global int* Ptr[] = {&Var};
...

In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol.

This also fixes LLD which was incorrectly generating a PCREL64 for this case.

Differential Revision: https://reviews.llvm.org/D38910

llvm-svn: 315936
2017-10-16 20:46:53 +00:00
Petr Hosek ac40140e24 [ELF] Recognize additional relocation types
These are generated by the linker itself and it shouldn't treat
them as unrecognized. This was introduced in r315552 and is triggering
an error when building UBSan shared library for i386.

Differential Revision: https://reviews.llvm.org/D38899

llvm-svn: 315737
2017-10-13 19:30:00 +00:00
Rui Ueyama be85529d2b Remove one parameter from Target::getRelExpr.
A section was passed to getRelExpr just to create an error message.
But if there's an invalid relocation, we would eventually report it
in relocateOne. So we don't have to pass a section to getRelExpr.

llvm-svn: 315552
2017-10-12 03:14:06 +00:00
Rui Ueyama 63e49d489b Rewrite comment.
llvm-svn: 315548
2017-10-12 02:09:11 +00:00
Rui Ueyama 67533a2cb3 Define RelType to represent relocation types.
We were using uint32_t as the type of relocation kind. It has a
readability issue because what Type really means in `uint32_t Type`
is not obvious. It could be a section type, a symbol type or a
relocation type.

Since we do not do any arithemetic operations on relocation types
(e.g. adding one to R_X86_64_PC32 doesn't make sense), it would be
more natural if they are represented as enums. Unfortunately, that
is not doable because relocation type definitions are spread into
multiple header files.

So I decided to use typedef. This still should be better than the
plain uint32_t because the intended type is now obvious.

llvm-svn: 315525
2017-10-11 22:49:24 +00:00
Alexander Richardson f52a3b94e1 [ELF][MIPS] Check for overflow when writing R_MIPS_CALL16 and R_MIPS_TLS_GOTTPREL
Summary:
These are 16 bit relocations and not part of a HI/LO pair so we need to
check that they don't overflow.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: ruiu, llvm-commits, emaste, sdardis

Tags: #lld

Differential Revision: https://reviews.llvm.org/D38614

llvm-svn: 315073
2017-10-06 16:15:59 +00:00
Simon Atanasyan f8db45361e [MIPS] Generate thunks for microMIPS code
If symbol has the STO_MIPS_MICROMIPS flag and requires a thunk to perform
call PIC from non-PIC functions, we need to generate a thunk with microMIPS
code.

llvm-svn: 314797
2017-10-03 13:30:02 +00:00
Simon Atanasyan 649e4d328f [MIPS] Fix PLT entries generation in case of linking regular and microMIPS code
Currently LLD calls the `isMicroMips` routine to determine type of PLT entries
needs to be generated: regular or microMIPS. This routine checks ELF
header flags in the `FirstObj` to retrieve type of linked object files.
So if the first file does not contain microMIPS code, LLD will generate
PLT entries with regular (non-microMIPS) code only.

Ideally, if a PLT entry is referenced by microMIPS code only this entry
should contain microMIPS code, if a PLT entry is referenced by regular
code this entry should contain regular code. In a "mixed" case the PLT
entry can be either microMIPS or regular, but each "cross-mode-call" has
additional cost.

It's rather difficult to implement this ideal solution. But we can
assume that if there is an input object file with microMIPS code, the
most part of the code is microMIPS too. So we need to deduce type of PLT
entries based on finally calculated ELF header flags and do not check
only the first input object file.

This change implements this.
  - The `getMipsEFlags` renamed to the `calcMipsEFlags`. The function
    called from the `LinkerDriver::link`. Result is stored in
    the Configuration::MipsEFlags field.
  - The `isMicroMips` and `isMipsR6` routines access the `MipsEFlags`
    field to get and check calculated ELF flags.
  - New types of PLT records created when necessary.

Differential revision: https://reviews.llvm.org/D37747

llvm-svn: 314675
2017-10-02 14:56:41 +00:00
Simon Atanasyan af273f203c [MIPS] Explicitly list supported relocations for MIPS target. NFC
This is change is inspired by the D28611 patch. New supported
relocations have been added to the switch statement.

llvm-svn: 313882
2017-09-21 14:40:32 +00:00
Davide Italiano bb0690e486 [AArch64] Properly check alignment for AARCH64_LD_PREL_LO19.
Follow-up suggested by Peter Smith.

llvm-svn: 313850
2017-09-21 00:26:28 +00:00
Davide Italiano f681a8fa3a [AArch64] Implement R_AARCH64_ LD_PREL_LO19.
Fixes PR34660.

Differential Revision:  https://reviews.llvm.org/D38053

llvm-svn: 313841
2017-09-20 23:49:50 +00:00
George Rimar 696a7f9ac6 [ELF] - Introduce std::vector<InputFile *> global arrays.
This patch removes lot of static Instances arrays from different input file 
classes and introduces global arrays for access instead. Similar to arrays we
have for InputSections/OutputSectionCommands.

It allows to iterate over input files in a non-templated code.

Differential revision: https://reviews.llvm.org/D35987

llvm-svn: 313619
2017-09-19 09:20:54 +00:00
Rafael Espindola 3d9f1c032a Add a helper for checking for weak undef. NFC.
llvm-svn: 313188
2017-09-13 20:43:04 +00:00
Simon Atanasyan 4f70b30d6f [MIPS] Initial support of microMIPS code linking
The patch implements initial support of microMIPS code linking:
  - Handle microMIPS specific relocations.
  - Emit both R1-R5 and R6 microMIPS PLT records.

For now linking mixed set of regular and microMIPS object files is not
supported. Also the patch does not handle (setup and clear) the
least-significant bit of an address which is utilized as the ISA mode
bit and allows to make jump between regular and microMIPS code without
any thunks.

Differential revision: https://reviews.llvm.org/D37335

llvm-svn: 313028
2017-09-12 13:08:24 +00:00
Peter Smith 20489ec563 [ELF] Always write non-immediate bits for AArch64 branch instruction.
To support errata patching on AArch64 we need to be able to overwrite
an arbitrary instruction with a branch. For AArch64 it is sufficient to
always write all the bits of the branch instruction and not just the
immediate field. This is safe as the non-immediate bits of the branch
instruction are always the same.

Differential Revision: https://reviews.llvm.org/D36745

llvm-svn: 312727
2017-09-07 16:29:52 +00:00
Peter Smith 1d5a070386 [ELF][AArch64] Add alignment checks for the LDST<N>_ABS_LO12_NC relocations
The R_AARCH64_LDST<N>_ABS LO12_NC relocations where N is 8, 16, 32, 64 or
128 have a scaled immediate. For example R_AARCH64_LDST32_ABS_LO12_NC
shifts the calculated value right by 4. If the target symbol + relocation
addend is not aligned properly then bits of the answer will be lost.

This change adds an alignment check to the relocations to make sure the
target of the relocation is aligned properly. This matches the behavior of
GNU ld. The motivation is to catch ODR violations such as a declaration of
extern int foo, but a definition of bool foo as the compiler may use
R_AARCH64_LDST32_ABS_LO12_NC for the former, but not align the destination.

Differential Revision: https://reviews.llvm.org/D37444

llvm-svn: 312637
2017-09-06 14:23:06 +00:00
Simon Atanasyan 7644191fb1 [MIPS] Convert template parameters to function arguments. NFC
Pass BSIZE and SHIFT as a function arguments to the `writeRelocation`
routine. It does not make a sense to have so many `writeRelocation's`
instances.

llvm-svn: 312495
2017-09-04 16:16:46 +00:00
Simon Atanasyan 351cf49579 [MIPS] Add curly brackets to improve code readability. NFC.
llvm-svn: 312494
2017-09-04 16:16:41 +00:00
George Rimar b2051f176c [ELF] - Fix comment. NFC.
llvm-svn: 312231
2017-08-31 10:14:10 +00:00
Simon Atanasyan 3876077ac7 [MIPS] Remove unused function's argument. NFC
llvm-svn: 311889
2017-08-28 14:40:53 +00:00
Simon Atanasyan 1998f859dc [MIPS] Merge multiple functions for writing relocation result into the single one. NFC
llvm-svn: 311712
2017-08-24 21:57:03 +00:00
Simon Atanasyan c5455e237f [MIPS] Keep all code read addends in the `getImplicitAddend` function
Currently LLD reads the R_MIPS_HI16's addends in the `computeMipsAddend`
function, the R_MIPS_LO16's addends in both `computeMipsAddend` and
`getImplicitAddend` functions. This patch moves reading all addends to
the `getImplicitAddend` function. As a side effect it fixes a "paired"
HI16/LO16 addend calculation if "LO16" part of a pair is not found.

llvm-svn: 311711
2017-08-24 21:56:58 +00:00
Simon Atanasyan 204cae99bb [MIPS] Remove redundant function getPcRelocAddend. NFC
llvm-svn: 311710
2017-08-24 21:56:52 +00:00
Rafael Espindola 3bab91332f Fix which file is in an error message.
When reporting an invalid relocation we were blaming the destination
file instead of the file with the relocation.

llvm-svn: 310084
2017-08-04 18:33:16 +00:00
Rui Ueyama 709fb2bb10 Rename ObjectFile -> ObjFile.
Rename it because it was too easy to conflict with llvm::object::ObjectFile
which broke buildbots several times.

llvm-svn: 309199
2017-07-26 22:13:32 +00:00
Rafael Espindola 244ef98161 Detemplate SymbolTable.
NFC, just makes it easier to access from non templated code.

llvm-svn: 309152
2017-07-26 18:42:48 +00:00
George Rimar 67c60727ce [ELF] - Apply clang-format. NFC.
llvm-svn: 308297
2017-07-18 11:55:35 +00:00
Peter Smith a49442f323 [ELF] Introduce target specific inBranchRange() function
In preparation for range extension thunks introduce a function that will
check whether a branch identified by a relocation type at a source address
can reach a destination.

For targets where range extension thunks are not supported the function will
return true as it is not expected that branches are out of range. An
implementation has been provided for ARM.

Differential Revision: https://reviews.llvm.org/D34690

llvm-svn: 308188
2017-07-17 16:54:29 +00:00
Rafael Espindola b04290569c Delete comparison with GlobalOffsetTable.
Now that _GLOBAL_OFFSET_TABLE_ is defined, we can just use R_PC for it
if needed.

llvm-svn: 306614
2017-06-28 23:19:32 +00:00
Rui Ueyama 0cc1483562 Add basic 64-bit SPARC support
Add support for the most common SPARC relocations.
Make DT_PLTGOT point to the PLT on SPARC.
Mark the PLT as executable on SPARC.

This adds a basic test that creates a SPARV9 executable
that invokes the exit system call on OpenBSD.

Patch by Mark Kettenis.

Differential Revision: https://reviews.llvm.org/D34618

llvm-svn: 306565
2017-06-28 17:05:39 +00:00
Rui Ueyama 921d43fbb2 Add trap instructions for ARM and MIPS.
This patch fills holes in executable sections with 0xd4 (ARM) or
0xef (MIPS). These trap instructions were suggested by Theo de Raadt.

llvm-svn: 306322
2017-06-26 19:45:53 +00:00
Peter Smith 113a59e7db [ELF] Define _GLOBAL_OFFSET_TABLE_ symbol relative to .got
On many architectures gcc and clang will recognize _GLOBAL_OFFSET_TABLE_ - .
and produce a relocation that can be processed without needing to know the
value of _GLOBAL_OFFSET_TABLE_. This is not always the case; for example ARM
gcc produces R_ARM_BASE_PREL but clang produces the more general
R_ARM_REL32 to _GLOBAL_OFFSET_TABLE_. To evaluate this relocation
correctly _GLOBAL_OFFSET_TABLE_ must be defined to be the either the base of
the GOT or end of the GOT dependent on architecture..

If/when llvm-mc is changed to recognize _GLOBAL_OFFSET_TABLE_ - . this
change will not be necessary for new objects. However there may still be
old objects and versions of clang.

Differential Revision: https://reviews.llvm.org/D34355

llvm-svn: 306282
2017-06-26 10:22:17 +00:00
Konstantin Zhuravlyov f3e3629f3d LLD: Move ELF/Mips.cpp to ELF/Arch/MipsArchTree.cpp
Differential Revision: https://reviews.llvm.org/D34358

llvm-svn: 305742
2017-06-19 21:03:57 +00:00
Rui Ueyama e145bc22fd Do not use make<> to allocate TargetInfo. NFC.
llvm-svn: 305577
2017-06-16 20:15:03 +00:00
Rui Ueyama c9fefaac67 Add comments for AVR support.
AVR support is somewhat exotic as generated ELF executables are not
directly consumed but objcopy'ed to write it to on-chip flush memory.
This comment describes it for those why a full-fledged ELF linker is
used to link programs for the 8-bit microcontroller.

llvm-svn: 305567
2017-06-16 17:53:26 +00:00
Rui Ueyama 21c0a9ceeb Split Target.cpp into small files.
Target.cpp contains code for all the targets that LLD supports. It was
simple and easy, but as the number of supported targets increased,
it got messy.

This patch splits the file into per-target files under ELF/arch directory.

Differential Revision: https://reviews.llvm.org/D34222

llvm-svn: 305565
2017-06-16 17:32:43 +00:00