Commit Graph

397 Commits

Author SHA1 Message Date
Benjamin Kramer 41112a1703 Move ARM specific test into the ARM subdir.
llvm-svn: 132255
2011-05-28 11:01:30 +00:00
Bruno Cardoso Lopes 787dfadc7c ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

llvm-svn: 132233
2011-05-27 23:46:09 +00:00
Bruno Cardoso Lopes 5445213a25 Fix PR9762
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

llvm-svn: 132026
2011-05-25 00:35:03 +00:00
Rafael Espindola 652bfdb1ab adds some attributes to attribute section when cpu is "xscale"
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

llvm-svn: 131751
2011-05-20 20:10:34 +00:00
Rafael Espindola 1866808384 fixes target address tBL and tBLX and sets relocation type
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)

Patch by koan-sin tan.

llvm-svn: 131748
2011-05-20 20:01:01 +00:00
Jason W Kim d0c937d4b2 This fixes one divergence between LLVM and binutils for ARM in the
text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

llvm-svn: 131674
2011-05-19 20:55:25 +00:00
Owen Anderson b745623b71 Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
llvm-svn: 131189
2011-05-11 17:00:48 +00:00
Jakob Stoklund Olesen 067ba3c23c Explicitly request -join-physregs for some tests that depend on it.
llvm-svn: 130855
2011-05-04 19:01:59 +00:00
Johnny Chen 33d3a9fadc Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.

llvm-svn: 128897
2011-04-05 18:02:46 +00:00
Bruno Cardoso Lopes bda3632bcd - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

llvm-svn: 128832
2011-04-04 17:18:19 +00:00
Bruno Cardoso Lopes ab8305063b Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128689
2011-03-31 23:26:08 +00:00
Daniel Dunbar 22c5560bc8 Remove stray empty test file.
llvm-svn: 128640
2011-03-31 17:01:56 +00:00
Bruno Cardoso Lopes c2452a6f1d Revert r128632 again, until I figure out what break the tests
llvm-svn: 128635
2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes 4c0aebfb91 Reapply r128585 without generating a lib depedency cycle. An updated log:
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632
2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay 73906b05ca Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
This revision introduced a dependency cycle, as nlewycky mentioned by email.

llvm-svn: 128597
2011-03-31 00:39:16 +00:00
Bruno Cardoso Lopes 280264b889 - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

llvm-svn: 128585
2011-03-30 23:32:32 +00:00
Bruno Cardoso Lopes f170f8bff6 Add asm parsing support w/ testcases for strex/ldrex family of instructions
llvm-svn: 128236
2011-03-24 21:04:58 +00:00
Rafael Espindola 1557fd6d39 Write the section table and the section data in the same order that
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.

llvm-svn: 127972
2011-03-20 18:44:20 +00:00
Owen Anderson 1d2f5cebe4 Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
llvm-svn: 127917
2011-03-18 22:50:18 +00:00
Cameron Zwarich 338d362200 Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127498
2011-03-11 21:52:04 +00:00
Daniel Dunbar 94ccb27b43 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
created from the", it broke some GCC test suite tests.

llvm-svn: 127477
2011-03-11 19:30:30 +00:00
Cameron Zwarich cc27b3acc4 Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459
2011-03-11 04:54:27 +00:00
Bill Wendling 5e57137e87 * Correct encoding for VSRI.
* Add tests for VSRI and VSLI.

llvm-svn: 127297
2011-03-09 00:33:17 +00:00
Bill Wendling a7f303de71 Correct the encoding for VRSRA and VSRA instructions.
llvm-svn: 127294
2011-03-09 00:00:35 +00:00
Bill Wendling e313f16ad9 * Fix VRSHR and VSHR to have the correct encoding for the immediate.
* Update the NEON shift instruction test to expect what 'as' produces.

llvm-svn: 127293
2011-03-08 23:48:09 +00:00
Bill Wendling a259686db1 A few more tests for instruction encodings.
llvm-svn: 127209
2011-03-08 02:51:48 +00:00
Bill Wendling 77ad1dc56d Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
2011-03-07 23:38:41 +00:00
Bill Wendling 3b1459b810 Narrow right shifts need to encode their immediates differently from a normal
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
2011-03-01 01:00:59 +00:00
Chris Lattner 78178749e9 split this test into arch specific pieces, so the ARM
test isn't run when the arm backend isn't built.  This
fixes PR9327

llvm-svn: 126500
2011-02-25 19:06:35 +00:00
Joerg Sonnenberger afb36fad99 Restore r125595 (reverted in r126336) with modifications:
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.

llvm-svn: 126443
2011-02-24 21:59:22 +00:00
Devang Patel b52040da17 Move arch specific tests in arch specific directories.
llvm-svn: 126401
2011-02-24 19:06:27 +00:00
Bruno Cardoso Lopes 9cd43977c3 Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr".

llvm-svn: 125948
2011-02-18 19:45:59 +00:00
Bruno Cardoso Lopes 90d1dfe4c6 Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489
2011-02-14 13:09:44 +00:00
Jim Grosbach 6e2e29bd11 Do AsmMatcher operand classification per-opcode.
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.

llvm-svn: 125245
2011-02-10 00:08:28 +00:00
Bruno Cardoso Lopes 36dd43fda6 Add support for parsing dmb/dsb instructions
llvm-svn: 125055
2011-02-07 22:09:15 +00:00
Jason W Kim 202630c6ee Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage
failures with relocations.

The code committed is a first cut at compatibility for emitted relocations in
ELF .o.

Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.

Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass

Added reminder fixme to tests for future conversion to .s form.

llvm-svn: 124996
2011-02-07 01:11:15 +00:00
Jason W Kim 4761fba833 Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to
5 to match the current doc.
Added FIXME reminder Make it really configurable later.

llvm-svn: 124899
2011-02-04 21:41:11 +00:00
Jason W Kim d2e2f56c36 Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
(yes, this is different from R_ARM_CALL)

- Adds a new method getARMBranchTargetOpValue() which handles the
  necessary distinction between the conditional and unconditional br/bl
  needed for ARM/ELF

At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...

Added a few FIXME's for future naming fixups in ARMInstrInfo.td

llvm-svn: 124895
2011-02-04 19:47:15 +00:00
Evan Cheng 2ea68db927 Fix test for non-darwin targets.
llvm-svn: 124640
2011-02-01 01:16:18 +00:00
Evan Cheng bb8420a070 Fix PLD encoding.
llvm-svn: 124458
2011-01-27 23:48:34 +00:00
Bruno Cardoso Lopes ce0af9c961 Add encoding testcases for ARM vcvtr variations
llvm-svn: 124289
2011-01-26 13:53:38 +00:00
Bruno Cardoso Lopes 178c1e0c9b fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
llvm-svn: 124288
2011-01-26 13:28:14 +00:00
Bruno Cardoso Lopes 4bd612384a Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975
2011-01-21 14:07:40 +00:00
Bruno Cardoso Lopes 1f69de3983 Add testcases for clz encoding
llvm-svn: 123937
2011-01-20 19:27:16 +00:00
Bruno Cardoso Lopes e965f06f7f Fix the encoding and parsing of clrex instruction
llvm-svn: 123936
2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes d8f9b37f31 Add cdp/cdp2 instructions for thumb/thumb2
llvm-svn: 123929
2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes 33461ecc82 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes 4d4b490fb7 Add mcr*2 and mr*c2 support to thumb2 targets
llvm-svn: 123919
2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes cf99dc7eb9 Add mcr* and mr*c support to thumb targets
llvm-svn: 123917
2011-01-20 16:35:57 +00:00
Bruno Cardoso Lopes d6335ce508 Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
llvm-svn: 123837
2011-01-19 16:56:52 +00:00
Owen Anderson dac7a0174e When matching asm operands, always try to match the most restricted type first.
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous.  This
is tricky to resolve since neither is a subset of the other.

XFAIL the test for now.  The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.

llvm-svn: 123786
2011-01-18 23:01:21 +00:00
Bruno Cardoso Lopes 2082057b18 Create two new generic classes to represent the following VMRS/VMSR variations:
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783
2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes cba727f291 Fix MRS encoding for arm and thumb.
llvm-svn: 123778
2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes e86a7ad01a Fix the encoding of t2ISB by using the right class and also parse it correctly
llvm-svn: 123776
2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes e6290ccf9b Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
llvm-svn: 123772
2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes 7f639c11d7 Add support for parsing and encoding ARM's official syntax for the BFI instruction
llvm-svn: 123770
2011-01-18 20:45:56 +00:00
Daniel Dunbar 66e91d4a58 McARM: Start marking T2 address operands as such, for the benefit of the parser.
llvm-svn: 123722
2011-01-18 03:06:03 +00:00
Evan Cheng d4a5c05c97 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.

llvm-svn: 123424
2011-01-14 02:38:49 +00:00
Evan Cheng 965b3c7323 Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369
2011-01-13 07:58:56 +00:00
Bill Wendling e6ff05c59d Sort the register list based on the *actual* register numbers rather than the
enum values we give to them. <rdar://problem/8823730>

llvm-svn: 123321
2011-01-12 21:20:59 +00:00
Jason W Kim 9c5b65d289 1. Support ELF pcrel relocations for movw/movt:
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294
2011-01-12 00:19:25 +00:00
Jason W Kim 1f7bc0707d Workaround for bug 8721.
.s Test added.

llvm-svn: 123292
2011-01-11 23:53:41 +00:00
Daniel Dunbar 9d944b3fcc McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the
carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

llvm-svn: 123238
2011-01-11 15:59:50 +00:00
Daniel Dunbar c0e8756ba9 McARM: Flush out hard coded known non-predicated mnemonic list.
llvm-svn: 123189
2011-01-10 21:01:03 +00:00
Bob Wilson fa27a8621c Add Neon VCVT instructions for f32 <-> f16 conversions.
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

llvm-svn: 121902
2010-12-15 22:14:12 +00:00
Bob Wilson c3ff538dcf Fix misspelled target triples in MC/ARM test commands.
llvm-svn: 121901
2010-12-15 22:14:01 +00:00
Kevin Enderby 4886cc8be7 Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

llvm-svn: 121830
2010-12-15 01:24:36 +00:00
Daniel Dunbar a9b9300bb8 MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
llvm-svn: 121772
2010-12-14 17:37:16 +00:00
Kevin Enderby 3164a346e6 Add support for parsing ARM arithmetic instructions that update or don't update
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.

llvm-svn: 121401
2010-12-09 19:19:43 +00:00
Jim Grosbach 567ebd0cb5 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
2010-12-03 22:31:40 +00:00
Owen Anderson 6187e66801 Add tests for more forms of Thumb2 loads and stores.
llvm-svn: 120436
2010-11-30 18:15:21 +00:00
Bill Wendling 811c936ed5 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
2010-11-30 07:44:32 +00:00
Owen Anderson e22c7322b8 Correct Thumb2 encodings for a much wider range of loads and stores.
llvm-svn: 120364
2010-11-30 00:14:31 +00:00
Owen Anderson 50d662b6cb Provide Thumb2 encodings for basic loads and stores.
llvm-svn: 120340
2010-11-29 22:44:32 +00:00
Bill Wendling 232e52cfb7 Add more Thumb encodings.
llvm-svn: 120279
2010-11-29 01:07:48 +00:00
Bill Wendling ccba1a8d95 More Thumb encodings.
llvm-svn: 120278
2010-11-29 01:00:43 +00:00
Bill Wendling 9600e97c60 Add Thumb encodings for REV instructions.
llvm-svn: 120277
2010-11-29 00:42:50 +00:00
Bill Wendling 775899eb2e Add more Thumb encodings.
llvm-svn: 120272
2010-11-29 00:18:15 +00:00
Bill Wendling c01d679928 Add encoding for ARM "trap" instruction.
llvm-svn: 119938
2010-11-21 11:05:29 +00:00
Bill Wendling 945b776b6e Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...

llvm-svn: 119774
2010-11-19 01:33:10 +00:00
Bill Wendling 2063b84297 Add support for parsing the writeback ("!") token.
llvm-svn: 119761
2010-11-18 23:43:05 +00:00
Owen Anderson 690fa953e1 More tests.
llvm-svn: 119756
2010-11-18 23:30:10 +00:00
Owen Anderson 3517585249 Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
llvm-svn: 119755
2010-11-18 23:29:56 +00:00
Owen Anderson 3fec5ff14b More Thumb2 encodings.
llvm-svn: 119737
2010-11-18 21:15:19 +00:00
Owen Anderson 3625098459 Fill out the set of Thumb2 multiplication operator encodings.
llvm-svn: 119733
2010-11-18 20:32:18 +00:00
Owen Anderson d127e7174b Try again at providing Thumb2 encodings for basic multiplication operators.
llvm-svn: 119601
2010-11-18 01:08:42 +00:00
Owen Anderson 28883834e1 Revert r119593 while I figure out my testing disagrees with the buildbot.
llvm-svn: 119597
2010-11-18 00:42:51 +00:00
Owen Anderson 64aaddcd64 Provide correct Thumb2 encodings for basic multiplication operators.
llvm-svn: 119593
2010-11-18 00:19:10 +00:00
Owen Anderson 55425e7f78 Second attempt at correct encodings for Thumb2 bitfield instructions.
llvm-svn: 119575
2010-11-17 22:16:31 +00:00
Owen Anderson 6c37ceb182 Revert r119551, which broke buildbots.
llvm-svn: 119555
2010-11-17 20:48:51 +00:00
Owen Anderson 7464116bde Provide Thumb2 encodings for bitfield instructions.
llvm-svn: 119551
2010-11-17 20:35:29 +00:00
Owen Anderson bced7ae046 More miscellaneous Thumb2 encodings.
llvm-svn: 119546
2010-11-17 19:57:38 +00:00
Bill Wendling 9898ac97fd Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460
2010-11-17 04:32:08 +00:00
Bill Wendling 92756fff57 Test encodings for LDM and STM.
llvm-svn: 119315
2010-11-16 01:38:20 +00:00
Owen Anderson 05a8daee21 Add Thumb2 encodings for mov and friends.
llvm-svn: 119295
2010-11-16 00:29:56 +00:00
Owen Anderson 7d97a99f4c Provide Thumb2 encodings for sxtb and friends.
llvm-svn: 119185
2010-11-15 21:12:05 +00:00
Owen Anderson 2a3c22efba Add Thumb2 encodings for comparison and shift operators.
llvm-svn: 119176
2010-11-15 19:58:36 +00:00
Owen Anderson 0e7d728327 Add correct Thumb2 encodings for mvn and friends.
llvm-svn: 119170
2010-11-15 18:45:17 +00:00
Owen Anderson 8fdd172502 First stab at providing correct Thumb2 encodings, start with adc.
llvm-svn: 118924
2010-11-12 21:12:40 +00:00
Owen Anderson ce2250fba4 Fill out support for Thumb2 encodings of NEON instructions.
llvm-svn: 118854
2010-11-11 23:12:55 +00:00
Owen Anderson 99a8cb4875 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
llvm-svn: 118843
2010-11-11 21:36:43 +00:00
Owen Anderson a56a2e1fc5 Flesh out tests for Thumb2 encodings of NEON instructions.
llvm-svn: 118837
2010-11-11 21:15:47 +00:00
Owen Anderson 7ffe3b35ac Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
More tests to come.

llvm-svn: 118819
2010-11-11 19:07:48 +00:00
Owen Anderson c7baee31ad Add support for ARM's specialized vector-compare-against-zero instructions.
llvm-svn: 118453
2010-11-08 23:21:22 +00:00
Owen Anderson 30c4892ea5 Add codegen and encoding support for the immediate form of vbic.
llvm-svn: 118291
2010-11-05 19:27:46 +00:00
Bill Wendling c002463ac4 Add encoding for VSTR.
llvm-svn: 118220
2010-11-04 00:59:42 +00:00
Owen Anderson bc9b31c493 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.

llvm-svn: 118204
2010-11-03 23:15:26 +00:00
Owen Anderson 0747307049 Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.

llvm-svn: 118201
2010-11-03 22:44:51 +00:00
Owen Anderson bb81f80af6 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183
2010-11-03 18:16:27 +00:00
Bill Wendling e84eb99cbb The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
2010-11-03 01:49:29 +00:00
Bill Wendling 603bd8f54c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
2010-11-02 22:31:46 +00:00
Owen Anderson dec87e10fd Provide correct encodings for the remaining vst variants that we currently generate.
llvm-svn: 118087
2010-11-02 22:18:18 +00:00
Owen Anderson b95618cfe0 Add correct encodings for basic variants for vst3 and vst4.
llvm-svn: 118082
2010-11-02 21:47:03 +00:00
Owen Anderson fa08e1e277 Add correct encodings for the basic variants for vst2.
llvm-svn: 118068
2010-11-02 21:16:58 +00:00
Owen Anderson 87c62e54e6 Add correct encodings for the basic form of vst1.
llvm-svn: 118067
2010-11-02 21:06:06 +00:00
Owen Anderson a83859539f Add correct encodings for the rest of the vld instructions that we generate.
llvm-svn: 118053
2010-11-02 20:40:59 +00:00
Owen Anderson 526ffd57d2 Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
llvm-svn: 117997
2010-11-02 01:24:55 +00:00
Owen Anderson ad40234eff Add correct NEON encodings for the "multiple single elements" form of vld.
llvm-svn: 117984
2010-11-02 00:05:05 +00:00
Bill Wendling 793af5fa07 Use ARM-style comments.
llvm-svn: 117955
2010-11-01 21:16:39 +00:00
Owen Anderson cd9da22f68 Use ARM-style comment syntax.
llvm-svn: 117941
2010-11-01 18:33:37 +00:00
Owen Anderson 083ddf7d6a Covert this test to .s form.
llvm-svn: 117939
2010-11-01 18:30:39 +00:00
Owen Anderson a7d985738c Convert this test to .s form.
llvm-svn: 117938
2010-11-01 18:26:43 +00:00
Owen Anderson e5271a935a Covert this test to .s form.
llvm-svn: 117937
2010-11-01 18:13:11 +00:00
Owen Anderson 051b7893dd Covert this test to .s form.
llvm-svn: 117935
2010-11-01 18:03:16 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler.
llvm-svn: 117929
2010-11-01 16:59:54 +00:00
Owen Anderson fccb9d032f Convert this test to .s form.
llvm-svn: 117900
2010-11-01 05:23:58 +00:00
Bill Wendling 193961bb1a Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.

llvm-svn: 117747
2010-10-29 23:50:21 +00:00
Owen Anderson 72dfc6a7c7 Convert this test to .s form.
llvm-svn: 117708
2010-10-29 20:39:19 +00:00
Owen Anderson 665b9e37ff Convert this test to .s form.
llvm-svn: 117704
2010-10-29 20:23:45 +00:00
Owen Anderson fe4b52a066 Convert this test to .s form.
llvm-svn: 117699
2010-10-29 20:17:07 +00:00
Owen Anderson 0093f9a634 Convert this test to .s form.
llvm-svn: 117696
2010-10-29 20:12:34 +00:00
Owen Anderson ede9d861db Covert this test to .s form.
llvm-svn: 117694
2010-10-29 19:56:07 +00:00
Owen Anderson 6f9cd06ff9 Convert this test to .s form.
llvm-svn: 117693
2010-10-29 19:51:11 +00:00
Owen Anderson 3ad831ac77 Convert this test to .s form.
llvm-svn: 117690
2010-10-29 19:45:32 +00:00
Owen Anderson 302596e5e1 Convert this test to .s form.
llvm-svn: 117689
2010-10-29 19:37:05 +00:00
Owen Anderson efdf57afdc Convert this test to .s form.
llvm-svn: 117686
2010-10-29 19:17:08 +00:00
Owen Anderson 221b524fe1 Convert this test to .s form.
llvm-svn: 117685
2010-10-29 19:09:08 +00:00
Owen Anderson b916206545 Covert this test to .s form.
llvm-svn: 117684
2010-10-29 19:05:26 +00:00
Owen Anderson 733d1b1a60 Convert this test to .s form.
llvm-svn: 117683
2010-10-29 18:58:30 +00:00
Owen Anderson 7d23a78188 Convert this test to .s form.
llvm-svn: 117682
2010-10-29 18:48:59 +00:00
Owen Anderson 7eed15242d Convert this file to less fragile .s form.
llvm-svn: 117681
2010-10-29 18:41:40 +00:00
Owen Anderson 13ff53e7b6 Replace this test with the less fragile .s version. Still XFAIL'd, since the ASM parser doesn't parse vabal yet.
llvm-svn: 117679
2010-10-29 18:31:26 +00:00
Owen Anderson 66aa87021c Covert this test to a .s file to reduce fragility.
llvm-svn: 117676
2010-10-29 18:18:40 +00:00
Owen Anderson b101af04b4 Convert this test to a .s file, so that it's not sensitive to codegen changes.
llvm-svn: 117633
2010-10-29 01:01:56 +00:00
Chris Lattner 5d6f6a061b add simple support for addrmode5 operands, allowing
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
2010-10-29 00:27:31 +00:00
Chris Lattner 327a61423b most simple arm instructions match correctly now,
it looks like we're not handling [] operands though

llvm-svn: 117607
2010-10-28 21:31:07 +00:00
Chris Lattner 1be0697ab9 fix the asmmatcher generator to handle targets with no RegisterPrefix
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
2010-10-28 21:28:42 +00:00
Evan Cheng 0165e25564 Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful.
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.

llvm-svn: 117530
2010-10-28 06:46:17 +00:00
Owen Anderson 2ef668840a Add correct NEON encodings for vtbl and vtbx.
llvm-svn: 117513
2010-10-28 00:18:46 +00:00
Owen Anderson 14be930317 Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
llvm-svn: 117512
2010-10-27 23:56:39 +00:00
Owen Anderson 9f371e7efa Tests for NEON encoding of vrev.
llvm-svn: 117502
2010-10-27 22:54:49 +00:00
Owen Anderson fadb951e5b Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
2010-10-27 22:49:00 +00:00
Owen Anderson ed9652f959 Provide correct encodings for the get_lane and set_lane variants of vmov.
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
Owen Anderson 40d24a4abf Provide correct NEON encodings for vdup.
llvm-svn: 117475
2010-10-27 19:25:54 +00:00
Owen Anderson fbdeab911a Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun.
llvm-svn: 117469
2010-10-27 18:17:12 +00:00
Owen Anderson 5fa98baef7 Tests for NEON encoding of vcls, vclz, and vcnt.
llvm-svn: 117466
2010-10-27 18:05:25 +00:00
Owen Anderson 6b5af599c0 Tests for NEON encoding of vneg and vqneg.
llvm-svn: 117463
2010-10-27 17:57:26 +00:00
Owen Anderson 1e5eb98ed8 Tests for NEON encoding of vabs and vqabs.
llvm-svn: 117460
2010-10-27 17:50:07 +00:00
Owen Anderson 8576a42cf3 Add correct NEON encodings for vsli and vsri.
llvm-svn: 117459
2010-10-27 17:40:08 +00:00
Owen Anderson d7e8135e1e Add correct NEON encodings for vsra and vrsra.
llvm-svn: 117458
2010-10-27 17:29:29 +00:00
Owen Anderson 825b2d1946 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
llvm-svn: 117411
2010-10-26 22:50:46 +00:00
Owen Anderson 2888e2c7f9 Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
llvm-svn: 117402
2010-10-26 21:58:41 +00:00
Owen Anderson c4126a1a2c Add tests for NEON encoding of vshll.
llvm-svn: 117399
2010-10-26 21:21:47 +00:00
Owen Anderson 0fbb20769f Tests for NEON encoding of vshr.
llvm-svn: 117396
2010-10-26 21:08:42 +00:00
Owen Anderson 3665fee8de Provide correct NEON encodings for vshl, register and immediate forms.
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
Owen Anderson db192ba90f Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts.
llvm-svn: 117385
2010-10-26 18:43:13 +00:00
Owen Anderson b3bcf529fc Tests for NEON encodings of vpmin and vpmax.
llvm-svn: 117382
2010-10-26 18:31:47 +00:00
Owen Anderson 691ce68d3c Add correct NEON encoding for vpadal.
llvm-svn: 117380
2010-10-26 18:18:03 +00:00
Owen Anderson 035b3261ee Tests for NEON encoding of vpadd and vpaddl.
llvm-svn: 117377
2010-10-26 18:04:51 +00:00
Owen Anderson 284cb361d1 Add NEON encodings for vmov and vmvn of immediates.
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
Bob Wilson e1961fe289 When the "true" and "false" blocks of a diamond if-conversion are the same,
do not double-count the duplicate instructions by counting once from the
beginning and again from the end.  Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end.  Radar 8589805.

This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction.  That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.

llvm-svn: 117333
2010-10-26 00:02:24 +00:00
Owen Anderson c0f777afbf Tests for NEON encoding of vmax.
llvm-svn: 117327
2010-10-25 23:45:34 +00:00
Owen Anderson 144c3f8c6a Tests for NEON encoding of vmin.
llvm-svn: 117326
2010-10-25 23:35:36 +00:00
Owen Anderson 1f6aad053d Add correct encodings for NEON vabal.
llvm-svn: 117315
2010-10-25 21:29:04 +00:00
Owen Anderson b9c91679aa Add correct NEON encodings for vaba.
llvm-svn: 117309
2010-10-25 20:52:57 +00:00
Owen Anderson 12214ddaa3 Tests for NEON encoding of vabdl.
llvm-svn: 117303
2010-10-25 20:36:28 +00:00
Owen Anderson 64aa05f865 Add tests for NEON encoding of vabd.
llvm-svn: 117302
2010-10-25 20:29:27 +00:00
Owen Anderson dd001b89d7 Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
llvm-svn: 117294
2010-10-25 20:17:22 +00:00
Owen Anderson dea09c7564 Provide correct NEON encodings for vbsl.
llvm-svn: 117293
2010-10-25 20:13:13 +00:00
Owen Anderson 2477446ee5 Add correct instruction encodings for vbic, vorn, and vmvn.
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
Owen Anderson dff239c5f9 Provide correct NEON encodings for vand, veor, and vorr.
llvm-svn: 117279
2010-10-25 18:28:30 +00:00
Owen Anderson d9cdda9ddc Add tests for NEON encoding of vtst.
llvm-svn: 117277
2010-10-25 18:10:34 +00:00
Owen Anderson feb3ee0c93 Add NEON encoding tests for vcgt and vacgt.
llvm-svn: 117276
2010-10-25 18:03:59 +00:00
Owen Anderson e5d0677173 Add tests for NEON encodings of vcge and vacge.
llvm-svn: 117274
2010-10-25 17:49:32 +00:00
Owen Anderson c178b80f65 Add a warning about our inability to test the encoding of vceq with immediate zero.
llvm-svn: 117273
2010-10-25 17:33:02 +00:00
Owen Anderson 02917f5b1b Add tests for NEON encoding of vceq.
llvm-svn: 117270
2010-10-25 17:20:26 +00:00
Owen Anderson a9ad6c0645 Add tests for NEON encoding of vsubhn and vrsubhn.
llvm-svn: 117269
2010-10-25 17:12:46 +00:00
Owen Anderson 358900d569 Add tests for NEON encoding of vqsub.
llvm-svn: 117214
2010-10-23 18:02:16 +00:00
Owen Anderson 92644efaf8 Add tests for NEON encoding of vhsub.
llvm-svn: 117189
2010-10-22 23:58:22 +00:00
Jim Grosbach 0ce06c08fb Add a CMP test.
llvm-svn: 117187
2010-10-22 23:48:01 +00:00
Owen Anderson f4e1a09d38 Add tests for NEON encoding of vsubw.
llvm-svn: 117186
2010-10-22 23:46:07 +00:00
Owen Anderson 9ef5c507ce Add tests for NEON encoding of vsubl.
llvm-svn: 117183
2010-10-22 23:36:36 +00:00
Owen Anderson c372775cc8 Add tests for NEON encoding of vsub.
llvm-svn: 117177
2010-10-22 23:21:04 +00:00
Owen Anderson cb5c1b75fe Add tests for NEON encoding of vqdmlsl.
llvm-svn: 117173
2010-10-22 23:08:47 +00:00
Owen Anderson d655a80774 Add tests for NEON encoding of vmlsl.
llvm-svn: 117171
2010-10-22 23:02:27 +00:00
Jim Grosbach b40a60fa2f tidy up.
llvm-svn: 117166
2010-10-22 22:15:48 +00:00
Jim Grosbach 2c9ae05c67 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
llvm-svn: 117165
2010-10-22 22:12:16 +00:00
Owen Anderson 3c4f72c9f8 Add tests for the correct encoding of NEON vmls.
llvm-svn: 117145
2010-10-22 20:31:24 +00:00
Owen Anderson 9d0122af7d Add correct NEON encodings for vqdmlal.
llvm-svn: 117134
2010-10-22 19:35:48 +00:00
Jim Grosbach 2b80543fc2 Add the encoding information for the rest of the ARM mode multiply instructions.
llvm-svn: 117133
2010-10-22 19:15:30 +00:00