fea7a44a9b
ARM assembly parsing and encoding tests for USAD8 and USADA8.
...
llvm-svn: 136284
2011-07-27 22:23:02 +00:00
1644409b47
ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
...
llvm-svn: 136282
2011-07-27 22:13:08 +00:00
1a3ddffc1c
Fix comment copy/paste-o.
...
llvm-svn: 136281
2011-07-27 22:11:41 +00:00
84ecab228a
ARM assembly parsing and encoding tests for UQASX and UQSAX.
...
llvm-svn: 136280
2011-07-27 22:09:30 +00:00
928f4175c0
ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
...
llvm-svn: 136279
2011-07-27 22:08:14 +00:00
39b062bfaa
ARM assembly parsing and encoding for UMULL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136277
2011-07-27 22:01:42 +00:00
0c398b9c7e
ARM assembly parsing and encoding for UMLAL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136274
2011-07-27 21:58:11 +00:00
121c21aba9
ARM assembly parsing and encoding tests for UMAAL.
...
llvm-svn: 136272
2011-07-27 21:53:42 +00:00
7cfd32a006
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
...
llvm-svn: 136267
2011-07-27 21:21:59 +00:00
3f45383ef5
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
...
llvm-svn: 136266
2011-07-27 21:20:45 +00:00
03f56d9de6
ARM parsing and encoding of SBFX and UBFX.
...
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
llvm-svn: 136264
2011-07-27 21:09:25 +00:00
36ce7492a6
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
...
llvm-svn: 136261
2011-07-27 20:43:44 +00:00
542333ea05
ARM assembly parsing and encoding tests for TST instruction.
...
llvm-svn: 136260
2011-07-27 20:38:58 +00:00
f176e1addb
ARM assembly parsing and encoding tests for TEQ instruction.
...
llvm-svn: 136259
2011-07-27 20:37:36 +00:00
fa9e6d43a0
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
...
llvm-svn: 136255
2011-07-27 20:29:48 +00:00
833b9d3353
ARM assembly parsing and encoding for extend instructions.
...
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
llvm-svn: 136252
2011-07-27 20:15:40 +00:00
edaa35ae6f
ARM diagnostics for ldrexd/stredx out of order paired register operands.
...
llvm-svn: 136110
2011-07-26 18:25:39 +00:00
4e895470bd
ARM parsing and encoding tests for load/store exclusive instructions.
...
llvm-svn: 136105
2011-07-26 18:07:21 +00:00
15e8d74231
ARM assembly parsing and encoding for SWP[B] instructions.
...
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
f16378479b
ARM parsing and encoding for SVC instruction.
...
llvm-svn: 136090
2011-07-26 16:24:27 +00:00
2c374c4fb6
ARM assembly parsing and encoding tests for SUB instruction.
...
llvm-svn: 136089
2011-07-26 15:44:05 +00:00
dc45f00cf5
Update ARM STM tests. Fix check: prefix for diagnostic tests.
...
llvm-svn: 136088
2011-07-26 15:41:22 +00:00
9becc53e32
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
...
llvm-svn: 136013
2011-07-25 23:32:14 +00:00
475c6dbef6
ARM assembly parsing and encoding for SSAT16 instruction.
...
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
3a9cbeed73
ARM assembly parsing and encoding for SSAT instruction.
...
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
llvm-svn: 135990
2011-07-25 22:20:28 +00:00
d69b3423a8
Add FIXME
...
llvm-svn: 135819
2011-07-22 22:15:38 +00:00
bc5d709ad9
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
...
llvm-svn: 135818
2011-07-22 22:13:00 +00:00
e7e1e163db
ARM assembly parsing and encoding updates.
...
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
llvm-svn: 135817
2011-07-22 22:06:05 +00:00
999afadffa
ARM assembly parsing and encoding tests.
...
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
llvm-svn: 135810
2011-07-22 21:34:56 +00:00
5b84e16503
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
...
llvm-svn: 135800
2011-07-22 20:51:24 +00:00
e2220221a2
ARM assembly parsing and encoding tests.
...
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
llvm-svn: 135798
2011-07-22 20:30:40 +00:00
8dfcc0bb92
ARM assembly parsing and encoding of SMLAL instruction.
...
Fix parsing of carry-setting variant SMLALS and add tests.
llvm-svn: 135797
2011-07-22 20:18:21 +00:00
d7c8c35301
ARM encoding and assembly parsing of SMLAD{X} instructions.
...
Fix encoding of destination register. Add tests.
llvm-svn: 135796
2011-07-22 20:11:20 +00:00
0b28f0cca2
ARM testcases for assembly parsing and encoding SMLA* instructions.
...
llvm-svn: 135795
2011-07-22 20:01:34 +00:00
d1f8bde10f
ARM assembly parsing and encoding for SMC instruction.
...
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
24ace20824
ARM encoding and assembly parsing tests.
...
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
llvm-svn: 135780
2011-07-22 18:04:48 +00:00
0a547701a4
ARM assembly parsing and encoding for SETEND instruction.
...
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
llvm-svn: 135776
2011-07-22 17:44:50 +00:00
4535b9194a
ARM assembly parsing and encoding tests for SEL instruction.
...
llvm-svn: 135772
2011-07-22 16:59:33 +00:00
3354674b48
ARM parsing and encoding tests for SBC instruction.
...
llvm-svn: 135718
2011-07-21 23:03:59 +00:00
8dbf59d041
ARM testcases for SADD/SASX parsing and encoding.
...
llvm-svn: 135715
2011-07-21 23:00:49 +00:00
2a0320c877
ARM assembly parsing support for RSC instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135713
2011-07-21 22:56:30 +00:00
17806e6636
ARM assembly parsing support for RSB instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135712
2011-07-21 22:37:43 +00:00
2a22c06267
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
...
llvm-svn: 135710
2011-07-21 22:29:23 +00:00
b31e60b7c6
ARM parsing and encodings tests for saturating arithmetic insns.
...
llvm-svn: 135709
2011-07-21 22:18:28 +00:00
0a8d89242f
ARM assembly parsing POP/PUSH mnemonics.
...
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
llvm-svn: 135702
2011-07-21 19:57:11 +00:00
b2aa2c4a24
Add tests for ARM PKH assembly parsing.
...
llvm-svn: 135696
2011-07-21 19:02:03 +00:00
2ea9f25f5f
Add parsing/encoding tests for ARM ORR instruction.
...
llvm-svn: 135602
2011-07-20 18:48:53 +00:00
a3fcb962eb
Consolidate ARM NOP encoding test.
...
llvm-svn: 135600
2011-07-20 18:39:38 +00:00
614e90a126
ARM parsing and encoding tests for MVN
...
llvm-svn: 135599
2011-07-20 18:37:08 +00:00
8d11490771
ARM assembly parsing of MUL instruction.
...
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
llvm-svn: 135596
2011-07-20 18:20:31 +00:00
d25c2cdad7
Tweak ARM assembly parsing and printing of MSR instruction.
...
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
llvm-svn: 135532
2011-07-19 22:45:10 +00:00
97094d8f06
ARM assembly parsing of MRS instruction.
...
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
llvm-svn: 135527
2011-07-19 21:59:29 +00:00
7d1e5f11ea
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
...
Add range checking to the immediate operands. Update tests accordingly.
llvm-svn: 135521
2011-07-19 20:35:35 +00:00
b17d9b12a6
Move mr[r]c[2] ARM tests and tidy up a bit.
...
llvm-svn: 135517
2011-07-19 20:28:56 +00:00
69721dce67
ARM testcases for MOVT.
...
llvm-svn: 135516
2011-07-19 20:23:25 +00:00
5cc3b4cd9a
ARM assembly parsing for MOV (register).
...
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
llvm-svn: 135513
2011-07-19 20:10:31 +00:00
7c09e3c3f3
ARM assembly parsing for MOV (immediate).
...
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
llvm-svn: 135500
2011-07-19 19:13:28 +00:00
20dd6e9fae
Whitespace.
...
llvm-svn: 135499
2011-07-19 19:02:39 +00:00
03a8a16f32
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
...
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
llvm-svn: 135203
2011-07-14 22:04:21 +00:00
51849920f1
Add some testcases for ARM MLA/MLS instructions.
...
llvm-svn: 135196
2011-07-14 21:43:05 +00:00
26e7449443
ARM MCRR/MCRR2 immediate operand range checking.
...
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
d37d2025e9
ARM MCR/MCR2 assembly parsing operand constraints.
...
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
llvm-svn: 135189
2011-07-14 21:19:17 +00:00
e336a290a6
Enable some tests we now handle correctly.
...
llvm-svn: 135185
2011-07-14 21:02:23 +00:00
2f9aeeef3b
Update ARM Assembly of LDM/STM.
...
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
llvm-svn: 135168
2011-07-14 18:35:38 +00:00
d616cf3497
ARM ISB assembly parsing tests.
...
llvm-svn: 135158
2011-07-14 18:02:25 +00:00
b218202586
ARM ISB instruction assembly parsing.
...
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
llvm-svn: 135156
2011-07-14 18:00:31 +00:00
e6f8b1fac6
ARM tests for EOR instruction parsing and encoding.
...
llvm-svn: 135119
2011-07-14 00:22:21 +00:00
f34e35da1c
Remove duplicate tests.
...
llvm-svn: 135117
2011-07-14 00:19:19 +00:00
a0958d7abf
ARM Assembler support for DSB instruction.
...
Add instalias for default 'sy' option. Add tests.
llvm-svn: 135116
2011-07-14 00:18:13 +00:00
44c3f08e85
ARM Assembler support for DMB instruction.
...
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
llvm-svn: 135109
2011-07-13 23:40:38 +00:00
507ba77465
ARM Assembler support for DBG instruction.
...
Add range checking and testing for parsing and encoding of DBG instruction.
llvm-svn: 135102
2011-07-13 22:59:38 +00:00
307de01867
ARM parsing and encoding tests for CMN/CMP.
...
llvm-svn: 135098
2011-07-13 22:26:58 +00:00
9559d360e5
Shuffle ARM assembly tests a bit.
...
llvm-svn: 135095
2011-07-13 22:19:10 +00:00
31756c2283
Range checking for CDP[2] immediates.
...
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
adb29b6dbb
Fix predicates for Thumb co-processor instructions.
...
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
llvm-svn: 135081
2011-07-13 21:14:23 +00:00
ec8989115d
Testcases for ARM assembly BX/BXJ instructions.
...
llvm-svn: 135078
2011-07-13 20:25:46 +00:00
2371a3f14a
Testcases for ARM assembly BLX/BL instructions.
...
llvm-svn: 135072
2011-07-13 20:11:04 +00:00
975b641ee8
Range checking for 16-bit immediates in ARM assembly.
...
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
c845e55374
Add tests for ARM parsing of 'BKPT' instruction.
...
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
43b45e2790
Fix copy-pasto.
...
llvm-svn: 135062
2011-07-13 19:16:30 +00:00
4f0f2ac757
Add tests for ARM parsing of 'BIC' instruction.
...
llvm-svn: 135061
2011-07-13 19:12:32 +00:00
6cfb1573bf
Add some FIXMEs.
...
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.
llvm-svn: 135060
2011-07-13 19:10:23 +00:00
b7cdd8772c
Add tests for ARM parsing of 'AND' instruction.
...
llvm-svn: 135056
2011-07-13 18:55:14 +00:00
bb24c595f7
Improve ARM assembly parsing diagnostics a bit.
...
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.
Add some tests for the diagnostics we do want.
llvm-svn: 135055
2011-07-13 18:49:30 +00:00
61a9f2af9e
Add tests for ARM parsing of 'ADD' instruction
...
llvm-svn: 135053
2011-07-13 18:12:46 +00:00
04afb071e1
Destination register operand is optional for ADC and SBC ARM.
...
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
7dcd1354f1
Flesh out ARM Parser support for shifted-register operands.
...
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
llvm-svn: 135049
2011-07-13 17:50:29 +00:00
992a2856f5
Add check for predicate w/o S bit.
...
llvm-svn: 134987
2011-07-12 16:25:04 +00:00
a9a3f0a414
Fix recognition of ARM 'adcs' mnemonic.
...
The 'CS' is not a predication suffix in this case.
llvm-svn: 134903
2011-07-11 17:09:57 +00:00
581da64241
Simplify printing of ARM shifted immediates.
...
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
llvm-svn: 134902
2011-07-11 16:48:36 +00:00
c5e6d2f519
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
...
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
llvm-svn: 134884
2011-07-11 03:57:24 +00:00
284b467d9f
Add support for ARM / Thumb mode switching with .code 16 and .code 32.
...
llvm-svn: 134760
2011-07-08 22:36:29 +00:00
8b2bda09a5
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
...
llvm-svn: 134590
2011-07-07 03:55:05 +00:00
16896325a6
ARM Thumb2 asm syntax optional destination operand for binary operators.
...
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff
rdar://9672867
llvm-svn: 133973
2011-06-28 00:19:13 +00:00
a6f7a1efcc
ARM Assembly support for Thumb mov-immediate.
...
Correctly parse the forms of the Thumb mov-immediate instruction:
1. 8-bit immediate 0-255.
2. 12-bit shifted-immediate.
The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.
llvm-svn: 133966
2011-06-27 23:54:06 +00:00
89bbfc434a
ARM assembler support for ldmfd/stmfd mnemonics.
...
llvm-svn: 133936
2011-06-27 20:32:18 +00:00
29882a75eb
ARM assembler support for vpush/vpop.
...
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.
rdar://9683231
llvm-svn: 133932
2011-06-27 20:00:07 +00:00
b5ee311602
ARM Assembly syntax support for arithmetic implied dest operand.
...
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
sub r2, r2, #6
sub r2, #6
rdar://9682597
llvm-svn: 133925
2011-06-27 19:09:15 +00:00
8fbb89ffa4
Move ARM-specific test to ARM directory.
...
Hopefully make the x86-target-only Windows bots happy.
llvm-svn: 133856
2011-06-25 01:53:17 +00:00
394f516d16
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
...
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
llvm-svn: 132324
2011-05-31 03:33:27 +00:00
Jim Grosbach