7db3bfbd45
ARM STRHT assembly parsing and encoding.
...
llvm-svn: 137358
2011-08-11 21:39:41 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
...
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
eb09f49a7f
ARM STRD assembly parsing and encoding.
...
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
2a50260f2f
ARM STRBT assembly parsing and encoding.
...
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
d0767f37c1
Add FIXME.
...
llvm-svn: 137336
2011-08-11 19:43:42 +00:00
295788756d
ARM STRB assembly parsing and encoding tests.
...
llvm-svn: 137335
2011-08-11 19:42:58 +00:00
14a4164206
Fix a copy/paste error so that LDRB(register) actually gets tested.
...
llvm-svn: 137333
2011-08-11 19:34:23 +00:00
06b7f0c901
ARM STR(register) assembly parsing and encoding tests.
...
llvm-svn: 137332
2011-08-11 19:26:17 +00:00
d564bf3181
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
27ad83d8a9
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
8ba76c6d5c
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
94ba2cba6e
ARM tests for LDRSHT assembly parsing and encoding.
...
llvm-svn: 137274
2011-08-10 23:18:30 +00:00
a6ab52bf9f
ARM tests for LDRSH assembly parsing and encoding.
...
llvm-svn: 137272
2011-08-10 23:12:25 +00:00
2953404723
ARM tests for LDRSBT assembly parsing and encoding.
...
llvm-svn: 137271
2011-08-10 23:08:56 +00:00
c11bbf3bda
ARM tests for LDRSB assembly parsing and encoding.
...
llvm-svn: 137270
2011-08-10 23:06:44 +00:00
35cdf36c32
Add FIXME.
...
llvm-svn: 137265
2011-08-10 22:56:43 +00:00
5e0c9711f2
ARM tests for LDRHT assembly parsing and encoding.
...
llvm-svn: 137263
2011-08-10 22:55:38 +00:00
7cd4253cc3
ARM tests for LDRH(register) assembly parsing and encoding.
...
llvm-svn: 137261
2011-08-10 22:45:42 +00:00
cd4dd255c0
ARM LDRH(immediate) assembly parsing and encoding support.
...
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
ae1b002fa3
Add FIXME
...
llvm-svn: 137258
2011-08-10 22:20:38 +00:00
1d9d5e93d1
ARM LDRD(register) assembly parsing and encoding.
...
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
5b96b80644
ARM LDRD(immediate) assembly parsing and encoding support.
...
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
cab35c0836
ARM parsing and encoding for LDRBT instruction.
...
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
llvm-svn: 137074
2011-08-08 23:28:47 +00:00
5838c0c47e
ARM parsing and encoding for LDRB instruction.
...
llvm-svn: 137071
2011-08-08 22:37:06 +00:00
f6dbc3a57c
Add FIXME.
...
llvm-svn: 137070
2011-08-08 22:11:33 +00:00
3d0b3a3a50
ARM load instruction shifted register index operands.
...
Parsing and encoding for shifted index operands for load instructions.
llvm-svn: 136986
2011-08-05 22:03:36 +00:00
c320c85261
ARM indexed load assembly parsing and encoding.
...
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
llvm-svn: 136982
2011-08-05 21:28:30 +00:00
0f2dd284e9
Add ARM LDR parsing tests.
...
llvm-svn: 136977
2011-08-05 20:33:39 +00:00
96df560ce1
print st_type with the correct number of bits.
...
llvm-svn: 136875
2011-08-04 15:24:00 +00:00
79ef75dc49
Print st_bind with the correct number of bits.
...
llvm-svn: 136874
2011-08-04 15:10:35 +00:00
1848231ad1
Print r_sym with the correct number of bits.
...
llvm-svn: 136873
2011-08-04 14:48:27 +00:00
260af5cef6
Print r_type with the correct number of bits.
...
llvm-svn: 136872
2011-08-04 14:39:30 +00:00
1b282e7e49
Another counter goes decimal.
...
llvm-svn: 136871
2011-08-04 14:27:46 +00:00
65c559c5fb
Change anther counter to decimal.
...
llvm-svn: 136870
2011-08-04 14:01:03 +00:00
cad9e7f094
Don't print a counter in hex.
...
llvm-svn: 136869
2011-08-04 13:39:15 +00:00
d359571120
ARM refactoring assembly parsing of memory address operands.
...
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
51726e2147
ARM SRS instruction parsing, diassembly and encoding support.
...
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
llvm-svn: 136509
2011-07-29 20:26:09 +00:00
c4dc52cd52
ARM assembly parsing and encoding for RFE instruction.
...
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
llvm-svn: 136479
2011-07-29 18:47:24 +00:00
1c1d2438aa
ARM update tests for CPS instruction.
...
llvm-svn: 136472
2011-07-29 17:39:27 +00:00
b9bebc1b03
CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
...
llvm-svn: 136408
2011-07-28 21:59:38 +00:00
a03ab0e3dc
ARM assembly parsing and encoding for BLX (immediate).
...
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
llvm-svn: 136406
2011-07-28 21:57:55 +00:00
7f45559e86
Remove obsolete FIXME reference in comment.
...
llvm-svn: 136400
2011-07-28 21:37:05 +00:00
864b609491
ARM assembly parsing and encoding for BFC and BFI.
...
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
llvm-svn: 136399
2011-07-28 21:34:26 +00:00
8b3184e540
ARM parsing and encoding for ADR.
...
The label does not have a '#' prefix. Add parsing and encoding tests.
llvm-svn: 136360
2011-07-28 16:33:54 +00:00
4356636fc0
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
...
llvm-svn: 136358
2011-07-28 16:00:41 +00:00
4059137f56
ARM parsing and encoding tests.
...
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.
llvm-svn: 136312
2011-07-28 00:37:03 +00:00
e37f7dc349
ARM assembly parsing and encoding for USUB16 and USUB8.
...
llvm-svn: 136289
2011-07-27 23:10:05 +00:00
05f80d3add
ARM assembly parsing and encoding for USAX.
...
llvm-svn: 136288
2011-07-27 23:07:00 +00:00
16dd4adcbe
Clean up tabs.
...
llvm-svn: 136286
2011-07-27 22:35:06 +00:00
57e2d3cb84
ARM assembly parsing and encoding support for USAT and USAT16.
...
Use range checked immediate operands for instructions. Add tests.
llvm-svn: 136285
2011-07-27 22:34:17 +00:00
Jim Grosbach