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5094 Commits

Author SHA1 Message Date
Chris Lattner 575352ac20 add vmladduhm 
llvm-svn: 27423
 2006-04-05 00:49:48 +00:00
Chris Lattner 5a528e565b Add m[tf]vscr instructions. 
llvm-svn: 27421
 2006-04-05 00:03:57 +00:00
Chris Lattner 0c82447c66 add a note 
llvm-svn: 27419
 2006-04-04 23:45:11 +00:00
Chris Lattner 281bb5da1d Add missing byte merges. 
llvm-svn: 27418
 2006-04-04 23:43:56 +00:00
Chris Lattner fc50ae521c Add FP -> Int Conversions 
llvm-svn: 27417
 2006-04-04 23:25:02 +00:00
Chris Lattner 96338b6a21 add average intrinsics 
llvm-svn: 27416
 2006-04-04 23:14:00 +00:00
Chris Lattner 4464383a17 add a note 
llvm-svn: 27414
 2006-04-04 22:43:55 +00:00
Chris Lattner 4a744e5c9d Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'. 
llvm-svn: 27413
 2006-04-04 22:28:35 +00:00
Evan Cheng 011c23d9d3 Added pslldq and psrldq. 
llvm-svn: 27412
 2006-04-04 21:49:39 +00:00
Evan Cheng 8f3b6b8d8a Minor fixes + naming changes. 
llvm-svn: 27410
 2006-04-04 19:12:30 +00:00
Evan Cheng 802b35c339 PSHUF* encoding bugs. 
llvm-svn: 27405
 2006-04-04 18:40:36 +00:00
Chris Lattner 95c7adc7cb Ask legalize to promote all vector shuffles to be v16i8 instead of having to 
handle all 4 PPC vector types.   This simplifies the matching code and allows
us to eliminate a bunch of patterns.  This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.

llvm-svn: 27400
 2006-04-04 17:25:31 +00:00
Evan Cheng e91e3bd874 cmpps / cmppd encoding bug 
llvm-svn: 27393
 2006-04-04 03:04:07 +00:00
Evan Cheng dd2eb27d6d Compact some intrinsic definitions. 
llvm-svn: 27388
 2006-04-04 00:10:53 +00:00
Chris Lattner b1e6d84544 Plug in the byte and short splats 
llvm-svn: 27387
 2006-04-04 00:05:13 +00:00
Chris Lattner 447a7968af Revert accidentally committed hunks. 
llvm-svn: 27386
 2006-04-03 23:58:04 +00:00
Chris Lattner 533aed9a35 Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand. 
llvm-svn: 27385
 2006-04-03 23:55:43 +00:00
Evan Cheng 0ef83c83e1 Some SSE1 intrinsics: min, max, sqrt, etc. 
llvm-svn: 27384
 2006-04-03 23:49:17 +00:00
Chris Lattner bf0016f2d4 revert previous patch 
llvm-svn: 27383
 2006-04-03 23:14:49 +00:00
Evan Cheng b64827e662 Use movlpd to: store lower f64 extracted from v2f64. 
Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382
 2006-04-03 22:30:54 +00:00
Chris Lattner 5400727595 Force use of a frame-pointer if there is anything on the stack that is aligned 
more than the OS keeps the stack aligned.

llvm-svn: 27381
 2006-04-03 22:03:29 +00:00
Evan Cheng ebf1006d16 - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. 
- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377
 2006-04-03 20:53:28 +00:00
Chris Lattner 78c788b450 Align vectors to the size in bytes, not bits. 
llvm-svn: 27376
 2006-04-03 19:28:50 +00:00
Chris Lattner 9ccd61c893 Add the full set of min/max instructions 
llvm-svn: 27372
 2006-04-03 15:58:28 +00:00
Andrew Lenharth df7abf8b74 support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4 
llvm-svn: 27370
 2006-04-03 04:19:17 +00:00
Andrew Lenharth 4e2c073a33 mul by const conversion sequences. more coming soon 
llvm-svn: 27368
 2006-04-03 03:18:59 +00:00
Andrew Lenharth 444bdb069a This makes McCat/12-IOtest go 8x faster or so 
llvm-svn: 27363
 2006-04-02 21:08:39 +00:00
Andrew Lenharth 01bd5523a3 This will be needed soon 
llvm-svn: 27362
 2006-04-02 20:13:57 +00:00
Chris Lattner acf1fc8a28 add a note 
llvm-svn: 27360
 2006-04-02 07:20:00 +00:00
Chris Lattner c5287c0ece Inform the dag combiner that the predicate compares only return a low bit. 
llvm-svn: 27359
 2006-04-02 06:26:07 +00:00
Chris Lattner 6c1321ca3f relax assertion 
llvm-svn: 27358
 2006-04-02 06:19:46 +00:00
Chris Lattner e6025525fb Allow targets to compute masked bits for intrinsics. 
llvm-svn: 27357
 2006-04-02 06:15:09 +00:00
Chris Lattner 80fdc1eb6b Remove done item 
llvm-svn: 27351
 2006-04-02 05:28:54 +00:00
Chris Lattner b80f114707 add a note 
llvm-svn: 27348
 2006-04-02 03:59:11 +00:00
Chris Lattner 7a29cf3c7f New note 
llvm-svn: 27337
 2006-04-02 01:47:20 +00:00
Chris Lattner 9b2d6e7886 Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into 
"vspltisb v0, 8" instead of a constant pool load.

llvm-svn: 27335
 2006-04-02 00:43:36 +00:00
Chris Lattner dc72c17798 Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor 
llvm-svn: 27331
 2006-04-01 22:41:47 +00:00
Chris Lattner 0baebb11bf ADd a note 
llvm-svn: 27324
 2006-04-01 04:08:29 +00:00
Chris Lattner ff77dc0a08 Shrinkify some more intrinsic definitions. 
llvm-svn: 27322
 2006-03-31 22:41:56 +00:00
Evan Cheng dc1161cf53 An entry about packed type alignments. 
llvm-svn: 27321
 2006-03-31 22:35:14 +00:00
Chris Lattner 20d3f3726f Pull operand asm string into base class, shrinkifying intrinsic definitions. 
No functionality change.

llvm-svn: 27320
 2006-03-31 22:34:05 +00:00
Evan Cheng a11d834b8c TargetData.cpp::getTypeInfo() was returning alignment of element type as the 
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).

llvm-svn: 27319
 2006-03-31 22:33:42 +00:00
Chris Lattner 110fc74b97 Fix 80 column violations :) 
llvm-svn: 27315
 2006-03-31 21:57:36 +00:00
Evan Cheng 5fd7c69473 Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed 
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314
 2006-03-31 21:55:24 +00:00
Evan Cheng 747e29ef0b Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}. 
llvm-svn: 27310
 2006-03-31 21:29:33 +00:00
Chris Lattner a4150f751d fix a pasto 
llvm-svn: 27308
 2006-03-31 21:19:06 +00:00
Chris Lattner e7fd4b0274 Add vperm support for all datatypes 
llvm-svn: 27307
 2006-03-31 20:00:35 +00:00
Chris Lattner baa73e0d91 Rearrange code a bit 
llvm-svn: 27306
 2006-03-31 19:52:36 +00:00
Chris Lattner 754b41c84b Add, sub and shuffle are legal for all vector types 
llvm-svn: 27305
 2006-03-31 19:48:58 +00:00
Evan Cheng cbffa4656b Add support to use pextrw and pinsrw to extract and insert a word element 
from a 128-bit vector.

llvm-svn: 27304
 2006-03-31 19:22:53 +00:00
Evan Cheng 3296f297d5 Add vector_extract and vector_insert nodes. 
llvm-svn: 27303
 2006-03-31 19:21:16 +00:00
Chris Lattner 40ff17dc22 add a note 
llvm-svn: 27302
 2006-03-31 19:00:22 +00:00
Chris Lattner 829a061abf note to self: *save* file, then check it in 
llvm-svn: 27291
 2006-03-31 06:04:53 +00:00
Chris Lattner d4058a59d4 Implement an item from the readme, folding vcmp/vcmp. instructions with 
identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll

llvm-svn: 27290
 2006-03-31 06:02:07 +00:00
Chris Lattner 070181c927 compactify some more instruction definitions 
llvm-svn: 27288
 2006-03-31 05:38:32 +00:00
Chris Lattner 45c709388a Compactify comparisons. 
llvm-svn: 27287
 2006-03-31 05:32:57 +00:00
Chris Lattner d7495ae7e9 Lower vector compares to VCMP nodes, just like we lower vector comparison 
predicates to VCMPo nodes.

llvm-svn: 27285
 2006-03-31 05:13:27 +00:00
Chris Lattner e5a6c4f8b7 These are done 
llvm-svn: 27284
 2006-03-31 04:53:21 +00:00
Chris Lattner 051f7861b8 Was returning the wrong type. 
llvm-svn: 27277
 2006-03-31 01:50:09 +00:00
Chris Lattner bca5fbe914 Mark INSERT_VECTOR_ELT as expand 
llvm-svn: 27276
 2006-03-31 01:48:55 +00:00
Evan Cheng 1b0d294de0 Expand all INSERT_VECTOR_ELT (obviously bad) for now. 
llvm-svn: 27275
 2006-03-31 01:30:39 +00:00
Chris Lattner f144dac7b7 Modify the TargetLowering::getPackedTypeBreakdown method to also return the 
unpromoted element type.

llvm-svn: 27273
 2006-03-31 00:46:36 +00:00
Evan Cheng d9d0bbb5ac Typo 
llvm-svn: 27272
 2006-03-31 00:33:57 +00:00
Evan Cheng 99d7205fba Ok for vector_shuffle mask to contain undef elements. 
llvm-svn: 27271
 2006-03-31 00:30:29 +00:00
Chris Lattner 549fb167eb Implement TargetLowering::getPackedTypeBreakdown 
llvm-svn: 27270
 2006-03-31 00:28:56 +00:00
Chris Lattner c4e3eadf21 Add the rest of the vmul instructions and the vmulsum* instructions. 
llvm-svn: 27268
 2006-03-30 23:39:06 +00:00
Chris Lattner a23158f1ca Use a new tblgen feature to significantly shrinkify instruction definitions that 
directly correspond to intrinsics.

llvm-svn: 27266
 2006-03-30 23:21:27 +00:00
Chris Lattner 551d3a11d3 Add a bunch of new instructions for intrinsics. 
llvm-svn: 27265
 2006-03-30 23:07:36 +00:00
Evan Cheng 7e2ff11a42 Make sure all possible shuffles are matched. 
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259
 2006-03-30 19:54:57 +00:00
Evan Cheng dd487d865b More logical ops patterns 
llvm-svn: 27257
 2006-03-30 07:33:32 +00:00
Evan Cheng c58ef7deeb Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 
llvm-svn: 27256
 2006-03-30 06:21:22 +00:00
Evan Cheng 593310016d Add 128-bit pmovmskb intrinsic support. 
llvm-svn: 27255
 2006-03-30 00:33:26 +00:00
Evan Cheng c5cf9bba05 Change SSE pack operation definitions to fit what the intrinsics expected. 
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254
 2006-03-29 23:53:14 +00:00
Evan Cheng b7fedffc78 - Added some SSE2 128-bit packed integer ops. 
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252
 2006-03-29 23:07:14 +00:00
Evan Cheng acc336475e Need to special case splat after all. Make the second operand of splat 
vector_shuffle undef.

llvm-svn: 27250
 2006-03-29 19:02:40 +00:00
Evan Cheng 3cf95747c7 Floating point logical operation patterns should match bit_convert. Or else 
integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248
 2006-03-29 18:47:40 +00:00
Evan Cheng 500ec16578 - More shuffle related bug fixes. 
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246
 2006-03-29 03:04:49 +00:00
Evan Cheng 3a1c4e75de Another entry about shuffles. 
llvm-svn: 27245
 2006-03-29 03:03:46 +00:00
Evan Cheng da59b0d2a8 - Only use pshufd for v4i32 vector shuffles. 
- Other shuffle related fixes.

llvm-svn: 27244
 2006-03-29 01:30:51 +00:00
Chris Lattner 7d6f4f14b4 add a note 
llvm-svn: 27243
 2006-03-29 00:24:13 +00:00
Evan Cheng 38b34296d0 Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics. 
The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240
 2006-03-28 23:51:43 +00:00
Evan Cheng 8160fd3d42 Fixing buggy code. 
llvm-svn: 27239
 2006-03-28 23:41:33 +00:00
Chris Lattner 66e1410858 add a note 
llvm-svn: 27227
 2006-03-28 18:56:23 +00:00
Jim Laskey d1aa1638c6 Expose base register for DwarfWriter. Refactor code accordingly. 
llvm-svn: 27225
 2006-03-28 13:48:33 +00:00
Jim Laskey 457e54efc1 Added missing paren on behalf of Ramana Radhakrishnan. 
llvm-svn: 27223
 2006-03-28 10:17:11 +00:00
Evan Cheng 21e5476deb Missed X86::isUNPCKHMask 
llvm-svn: 27222
 2006-03-28 08:27:15 +00:00
Evan Cheng be2d9a0e99 movlps and movlpd should be modeled as two address code. 
llvm-svn: 27221
 2006-03-28 07:01:28 +00:00
Evan Cheng dc57ae0711 Update 
llvm-svn: 27220
 2006-03-28 06:55:45 +00:00
Evan Cheng 4e7374ff8a Typo 
llvm-svn: 27219
 2006-03-28 06:53:49 +00:00
Evan Cheng 1a194a5264 * Prefer using operation of matching types. e.g unpcklpd rather than movlhps. 
* Bug fixes.

llvm-svn: 27218
 2006-03-28 06:50:32 +00:00
Nate Begeman af8c373e77 Fix a couple typos 
llvm-svn: 27216
 2006-03-28 04:18:18 +00:00
Nate Begeman 1b3928765d Add a few more altivec intrinsics 
llvm-svn: 27215
 2006-03-28 04:15:58 +00:00
Evan Cheng 08b473c619 Added a couple of entries about movhps and movlhps. 
llvm-svn: 27212
 2006-03-28 02:49:12 +00:00
Evan Cheng 3765fadef6 All unpack cases are now being handled. 
llvm-svn: 27211
 2006-03-28 02:44:05 +00:00
Evan Cheng 2bc3280659 - Clean up / consoladate various shuffle masks. 
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210
 2006-03-28 02:43:26 +00:00
Chris Lattner 3710fca2b8 implement a bunch more intrinsics. 
llvm-svn: 27209
 2006-03-28 02:29:37 +00:00
Chris Lattner cb5ec07cc3 Use normal lvx for scalar_to_vector instead of lve*x. They do the exact 
same thing and we have a dag node for the former.

llvm-svn: 27205
 2006-03-28 01:43:22 +00:00
Chris Lattner e55d171ccd Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. 
llvm-svn: 27201
 2006-03-28 00:40:33 +00:00
Evan Cheng 5df75889db Model unpack lower and interleave as vector_shuffle so we can lower the 
intrinsics as such.

llvm-svn: 27200
 2006-03-28 00:39:58 +00:00
Jim Laskey fa53b276d0 Translate llvm target registers to dwarf register numbers properly. 
llvm-svn: 27180
 2006-03-27 20:18:45 +00:00