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5 Commits

Author SHA1 Message Date
Matt Arsenault cc88ce36ed AMDGPU: Add instruction definitions for VGPR indexing 
VI added a second method of indexing into VGPRs
besides using v_movrel*

llvm-svn: 284027
 2016-10-12 18:00:51 +00:00
Matt Arsenault 7b1dc2c983 AMDGPU: Use i64 scalar compare instructions 
VI added eq/ne for i64, so use them.

llvm-svn: 281800
 2016-09-17 02:02:19 +00:00
Nikolay Haustov cb9dddb1d7 [AMDGPU] Assembler: Update SOP* tests 
Add VI encodings.
Reformat sopp.s to match style of other files.

Differential Revision: http://reviews.llvm.org/D18084

llvm-svn: 263540
 2016-03-15 07:44:57 +00:00
Nikolay Haustov 79af6b33e0 [AMDGPU] Assembler: SOP* instruction fixes 
s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit.
s_rfe_b64 has just one destination operand and no source.
Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that.
Add s_memrealtime test and change comments in smem.s to follow common style.
Change test for s_memtime to use non-zero register to make it really test encoding.
Add tests for s_buffer_load*.
Add tests for SOPC instructions (same for SI and VI)

Differential Revision: http://reviews.llvm.org/D18040

llvm-svn: 263420
 2016-03-14 11:17:19 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00