Commit Graph

118899 Commits

Author SHA1 Message Date
Rafael Espindola 097110f590 Continue to remove the notion that ELF has dynamic and static symbols.
The ELFObjectFile now just reasons about a section/index pair, removing
one of the users that force ELF.h to maintain the difference.

llvm-svn: 241344
2015-07-03 12:00:05 +00:00
NAKAMURA Takumi 7779f75cc8 llvm/test/CodeGen/ARM/fnattr-trap.ll: Add -mtriple, to appease targeting *-win32.
LLVM ERROR: CPU: 'generic' does not support ARM mode execution!

llvm-svn: 241329
2015-07-03 08:21:38 +00:00
Simon Pilgrim 6a8e75c735 whitespace tidyup. NFC.
llvm-svn: 241326
2015-07-03 08:02:12 +00:00
Simon Pilgrim b504263e4a [X86][SSE] Sign extension for target vector sizes less than 128 bits (pt2)
Add support for v2i8/v2i16 to v2f64 by using a sign extension to v2i32 before conversion to v2f64.

Differential Revision: http://reviews.llvm.org/D10589

llvm-svn: 241325
2015-07-03 08:01:36 +00:00
Yaron Keren 5dbf346c52 Initialize booleans CallsUnwindInit and CallsEHReturn with false instead of 0.
llvm-svn: 241324
2015-07-03 07:56:24 +00:00
Simon Pilgrim 385bf00ea2 [X86][SSE] Sign extension for target vector sizes less than 128 bits (pt1)
This patch adds support for sign extension for sub 128-bit vectors, such as to v2i32. It concatenates with UNDEF subvectors up to 128-bits, performs the sign extension (i.e. as v4i32) and then extracts the target subvector.

Patch 1/2 of D10589 - the second patch covers the conversion of v2i8/v2i16 to v2f64.

llvm-svn: 241323
2015-07-03 07:51:01 +00:00
Nadav Rotem 754eb7c563 Fix an overly aggressive assertion in getCopyFromPartsVector.
The assertion in getCopyFromPartsVector assumed that the vector 'part' must
match the type of argument (arguments are potentially split into multiple
parts). However, in some cases the targets return a 'part' of the right size
but with a different type. We already handle this case correctly later on
and generate a bitcast. This commit just makes sure that we are actually
checking the property that we care about.

llvm-svn: 241312
2015-07-02 23:23:52 +00:00
Adrian Prantl 18c073ad6b DIBuilder: Now that DICompileUnit is distinct, stop using temporary nodes
for the arrays.

llvm-svn: 241308
2015-07-02 22:32:52 +00:00
Akira Hatanaka 56c70441dc Use function attribute "trap-func-name" and remove TargetOptions::TrapFuncName.
This commit changes normal isel and fast isel to read the user-defined trap
function name from function attribute "trap-func-name" attached to llvm.trap or
llvm.debugtrap instead of from TargetOptions::TrapFuncName. This is needed to
use clang's command line option "-ftrap-function" for LTO and enable changing
the trap function name on a per-call-site basis.

Out-of-tree projects currently using TargetOptions::TrapFuncName to specify the
trap function name should attach attribute "trap-func-name" to the call sites
of llvm.trap and llvm.debugtrap instead.

rdar://problem/21225723

Differential Revision: http://reviews.llvm.org/D10832

llvm-svn: 241305
2015-07-02 22:13:27 +00:00
Akira Hatanaka 5c40eeabef Add functions for adding and testing string attributes to CallInst. NFC.
This change is needed later when I make changes to attach string function
attributes to llvm.trap and llvm.debugtrap.

llvm-svn: 241304
2015-07-02 22:08:48 +00:00
Dan Gohman bfaf7e15d1 [WebAssembly] Set the HasFloatingPointExceptions flag for WebAssembly.
llvm-svn: 241302
2015-07-02 21:36:25 +00:00
Rafael Espindola d0212cd46c Try to fix the build of IntelJITEventListener.
llvm-svn: 241301
2015-07-02 21:24:12 +00:00
Rafael Espindola 5d0c2ffadf Return ErrorOr from SymbolRef::getName.
This function can really fail since the string table offset can be out of
bounds.

Using ErrorOr makes sure the error is checked.

Hopefully a lot of the boilerplate code in tools/* can go away once we have
a diagnostic manager in Object.

llvm-svn: 241297
2015-07-02 20:55:21 +00:00
Bill Schmidt a1c30053e7 [PPC64LE] Remove implicit-subreg restriction from VSX swap removal
In r241285, I removed the SUBREG_TO_REG restriction from VSX swap
removal, determining that this was overly conservative.  We have
another form of the same restriction in that we check for the presence
of implicit subregs in vector operations.  As with SUBREG_TO_REG for
partial register conversions, an implicit subreg is safe in and of
itself, provided no other operation makes a lane-sensitive assumption
about the result.  This patch removes that restriction, by removing
the HasImplicitSubreg flag and all code that relies on it.

I've added a test case that fails to optimize before this patch is
applied, and optimizes properly with the patch.  Test based on a
report from Anton Blanchard.

llvm-svn: 241290
2015-07-02 19:01:22 +00:00
Sanjoy Das b1ca4eb6ae [Statepoints] Make operator bool() explicit.
(Addressing post-commit review.)

llvm-svn: 241288
2015-07-02 18:15:18 +00:00
Rafael Espindola 03e23121f8 Remove a report_fatal_error that should be unreachable.
If we created a relocation iterator, we have a valid relocation section.

llvm-svn: 241286
2015-07-02 17:16:07 +00:00
Bill Schmidt 7c691fee1c [PPC64LE] Teach swap optimization about the doubleword splat idiom
With a previous patch, the VSX swap optimization is able to recognize
the doubleword load-splat idiom that can be implemented using lxvdsx.
However, that does not cover a doubleword splat where the source is a
register.  We can implement this using xxspltd (a special form of
xxpermdi).  This patch teaches the swap optimization pass about this
idiom.

As a prerequisite, it also permits swap optimization to succeed for
all forms of SUBREG_TO_REG.  Previously we were conservative and only
allowed SUBREG_TO_REG when it copied a full register.  However, on
reflection any form of SUBREG_TO_REG is safe in and of itself, so long
as an unsafe operation is not performed on its result.  In particular,
a widening SUBREG_TO_REG often occurs as an input to a doubleword
splat idiom, particularly in auto-vectorized code.

The doubleword splat idiom is an XXPERMDI operation where both source
registers are identical, and the selection mask is either 0 (splat the
first element) or 3 (splat the second element).  To determine whether
the registers are identical, we use the existing mechanism for looking
through "copy-like" operations.  That mechanism has a side effect of
marking the XXPERMDI operation as using a physical register, which
would invalidate its presence in a swap-optimized region.  This is
correct for the form of XXPERMDI that performs a swap and hence would
be removed, but is not what we want for a doubleword-splat variety of
XXPERMDI.  Therefore we reset the physical-register flag on the
XXPERMDI when it represents a splat.

A simple test case is added to verify that we generate the splat and
that we also remove the xxswapd instructions that would otherwise be
associated with the load and store of another operand.

llvm-svn: 241285
2015-07-02 17:03:06 +00:00
Rafael Espindola 2cd195166f Convert a member variable to a local one.
llvm-svn: 241284
2015-07-02 16:59:57 +00:00
Gabor Ballabas 5fe650c5e1 Reworking the test part of r241149
The test part of r241149 has been reverted in r241451, due to misplaced test cases.
This patch splits those test cases among the appropriate targets.

Differential Revision: http://reviews.llvm.org/D10897

llvm-svn: 241283
2015-07-02 16:53:23 +00:00
Rafael Espindola 4e7212177f Fix for PR23310: llvm-dis crashes when trying to upgrade an intrinsic.
When trying to upgrade @llvm.x86.sse2.psrl.dq while parsing a module,
BitcodeReader adds the function to its worklist twice, resulting in a
crash when accessing it the second time.

This patch replaces the worklist vector by a map.

Patch by Philip Pfaffe.

llvm-svn: 241281
2015-07-02 16:22:40 +00:00
Rafael Espindola d80c526e74 Handle .dynsym a bit more like we handle .symtab.
They have the same format and we find them in the same way, no reason to handle
them differently.

llvm-svn: 241280
2015-07-02 16:03:38 +00:00
Rafael Espindola 86e3340f31 Rangify some loops.
Patch by Philip Pfaffe!

llvm-svn: 241279
2015-07-02 15:55:09 +00:00
Rafael Espindola 668048cea7 Use default member initializes. NFC.
llvm-svn: 241277
2015-07-02 15:48:05 +00:00
Leny Kholodov bebb27b0d2 [Support] Lazy load of dbghlp.dll on Windows
This patch changes linkage with dbghlp.dll for clang from static (at load time)
to on demand (at the first use of required functions). Clang uses dbghlp.dll
only in minor use-cases. First of all in case of crash and in case of plugin load.
The dbghlp.dll library can be absent on system. In this case clang will fail
to load. With lazy load of dbghlp.dll clang can work even if dbghlp.dll
is not available.

Differential Revision: http://reviews.llvm.org/D10737

llvm-svn: 241271
2015-07-02 14:34:57 +00:00
Michael Kuperstein 16d307fb80 [X86] Convert an instruction relaxation test to use objdump instead of readobj
Patch by: david.l.kreitzer@intel.com

llvm-svn: 241270
2015-07-02 14:27:35 +00:00
Rafael Espindola e7b37f1401 Move error checking from once per relocation to once per relocation section.
llvm-svn: 241269
2015-07-02 14:27:07 +00:00
Yaron Keren 6967cbb319 Remove whitespace from start of line, NFC.
llvm-svn: 241268
2015-07-02 14:25:09 +00:00
Rafael Espindola 7f162ec2cc Expose getRel and getRela to reduce code duplication.
llvm-svn: 241266
2015-07-02 14:21:38 +00:00
Yaron Keren afe39833ce Delete whitespace at start of line.
llvm-svn: 241265
2015-07-02 14:17:12 +00:00
Rafael Espindola 2119a96279 Improve error message.
Thanks to Sean Silva for the suggestion.

llvm-svn: 241255
2015-07-02 11:48:48 +00:00
Pawel Bylica c52eabb285 Reapply r240291: Fix shl folding in DAG combiner.
The code responsible for shl folding in the DAGCombiner was assuming incorrectly that all constants are less than 64 bits. This patch simply changes the way values are compared.

It has been reverted previously because of some problems with comparing APInt with raw uint64_t. That has been fixed/changed with r241204.

llvm-svn: 241254
2015-07-02 11:44:54 +00:00
Charlie Turner 0912de3216 [GraphWriter] Don't wait on xdg-open when not on Apple.
By default, the GraphWriter code assumes that the generic file open
program (`open` on Apple, `xdg-open` on other systems) can wait on the
forked proces to complete. When the fork ends, the code would delete
the temporary dot files created, and return.

On GNU/Linux, the xdg-open program does not have a "wait for your fork
to complete before dying" option. So the behaviour was that xdg-open
would launch a process, quickly die itself, and then the GraphWriter
code would think its OK to quickly delete all the temporary files.
Once the temporary files were deleted, the dot viewers would get very
upset, and often give you weird errors.

This change only waits on the generic open program on Apple platforms.
Elsewhere, we don't wait on the process, and hence we don't try and
clean up the temporary files.

llvm-svn: 241250
2015-07-02 09:32:07 +00:00
Charlie Turner 5b41ea0d56 [NFC] Minor editorial fixes to the CodeGen docs.
llvm-svn: 241249
2015-07-02 09:32:01 +00:00
Sanjoy Das bbb2e8234c [NFC] Make the Statepoint class more like CallSite
Summary: Rename some methods to make Statepoint look more like CallSite.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10756

llvm-svn: 241235
2015-07-02 02:53:45 +00:00
Sanjoy Das aadda823b4 [Statepoints][NFC] Constify accessors on Statepoint.
Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10755

llvm-svn: 241234
2015-07-02 02:53:41 +00:00
Sanjoy Das d79add5c28 [Statepoints][NFC] Rename variables to llvm style.
Summary:
(I don't think this change needs review, this was uploaded to
phabricator to provide context for later dependent changes.)

Differential Revision: http://reviews.llvm.org/D10630

llvm-svn: 241233
2015-07-02 02:53:39 +00:00
Sanjoy Das a8fd329d22 [Statepoints][NFC] Add Statepoint::operator bool()
Summary:
This allows the "if (Statepoint SP = Statepoint(I))" idiom.

(I don't think this change needs review, this was uploaded to
phabricator to provide context for later dependent changes.)

Differential Revision: http://reviews.llvm.org/D10629

llvm-svn: 241232
2015-07-02 02:53:36 +00:00
Sanjoy Das 2f371f978f [Statepoints][NFC] Add Statepoint::getGCResult.
Summary:
Introduce a simple accessor to get the gc_result hanging off of a
statepoint.

(I don't think this change needs review, this was uploaded to
phabricator to provide context for later dependent changes.)

Differential Revision: http://reviews.llvm.org/D10627

llvm-svn: 241231
2015-07-02 02:53:34 +00:00
Sanjoy Das 7869d4b846 [LazyCallGraph] Port test case from r240039 to LCG.
Summary:
r240039 adds a test case to check that CallGraph does the right thing
with respect to non-leaf intrinsics like statepoint and patchpoint.
This ports the same test case to LazyCallGraph.  LazyCallGraph already
does the right thing with respect to escaping function pointers so there
is no need to change any code.

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10582

llvm-svn: 241226
2015-07-02 02:03:58 +00:00
Eric Christopher ced3032be5 Make an X86 specific directory and put the recent X86 tti specific
inlining test into it.

llvm-svn: 241223
2015-07-02 01:36:31 +00:00
Eric Christopher e100226879 Implement TargetTransformInfo::hasCompatibleFunctionAttributes for X86.
This checks subtarget feature compatibility for inlining by verifying
that the callee is a strict subset of the caller's features. This includes
the cpu as part of the subtarget we can get via the incoming functions as
the backend takes CPUs as feature sets.

This allows us to inline things like:

int foo() { return baz(); }

int __attribute__((target("sse4.2"))) bar() {
  return foo();
}

so that generic code can be inlined into specialized functions.

llvm-svn: 241221
2015-07-02 01:11:50 +00:00
Eric Christopher 4371b13937 Add a routine to TargetTransformInfo that will allow targets to look
at the attributes on a function to determine whether or not to allow
inlining.

llvm-svn: 241220
2015-07-02 01:11:47 +00:00
JF Bastien 03855df197 WebAssembly: start instructions
Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

llvm-svn: 241211
2015-07-01 23:41:25 +00:00
Quentin Colombet 9729fb3315 [TwoAddressInstructionPass] Try 3 Addr Conversion After Commuting.
TwoAddressInstructionPass stops after a successful commuting but 3 Addr
conversion might be good for some cases.
 
Consider:

int foo(int a, int b) {
  return a + b;
}

Before this commit, we emit:

addl	%esi, %edi
movl	%edi, %eax
ret

After this commit, we try 3 Addr conversion:

leal	(%rsi,%rdi), %eax
ret

Patch by Volkan Keles <vkeles@apple.com>!

Differential Revision: http://reviews.llvm.org/D10851

llvm-svn: 241206
2015-07-01 23:12:13 +00:00
Pawel Bylica ea46a66ea2 Change APInt comparison with uint64_t.
Summary:
This patch changes the way APInt is compared with a value of type uint64_t.
Before the uint64_t value was truncated to the size of APInt before comparison.
Now the comparison takes into account full 64-bit precision.

Test Plan: Unit tests added. No regressions. Self-hosted check-all done as well.

Reviewers: chandlerc, dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10655

llvm-svn: 241204
2015-07-01 22:56:43 +00:00
Matthias Braun e21e0f1620 Test for specific output in lit test
llvm-svn: 241200
2015-07-01 22:34:59 +00:00
Alexey Samsonov 958dab71b3 [LoopVectorize] Use ReplaceInstWithInst() helper where appropriate.
This is mostly an NFC, which increases code readability (instead of
saving old terminator, generating new one in front of old, and deleting
old, we just call a function). However, it would additionaly copy
the debug location from old instruction to replacement, which
would help PR23837.

llvm-svn: 241197
2015-07-01 22:18:30 +00:00
Pete Cooper abcac11d1b Pack MCSymbol::Flags in to the bitfield with other members. NFC.
All file formats only needed 16-bits right now which is enough to fit
in to the padding with other fields.

This reduces the size of MCSymbol to 24-bytes on a 64-bit system.  The
layout is now

   0 | class llvm::MCSymbol
   0 |   class llvm::PointerIntPair SectionOrFragmentAndHasName
   0 |     intptr_t Value
     |   [sizeof=8, dsize=8, align=8
     |    nvsize=8, nvalign=8]

   8 |   unsigned int IsTemporary
   8 |   unsigned int IsRedefinable
   8 |   unsigned int IsUsed
   8 |   _Bool IsRegistered
   8 |   unsigned int IsExternal
   8 |   unsigned int IsPrivateExtern
   8 |   unsigned int Kind
   9 |   unsigned int IsUsedInReloc
   9 |   unsigned int SymbolContents
   9 |   unsigned int CommonAlignLog2
  10 |   uint32_t Flags
  12 |   uint32_t Index
  16 |   union
  16 |     uint64_t Offset
  16 |     uint64_t CommonSize
  16 |     const class llvm::MCExpr * Value
     |   [sizeof=8, dsize=8, align=8
     |    nvsize=8, nvalign=8]

     | [sizeof=24, dsize=24, align=8
     |  nvsize=24, nvalign=8]

llvm-svn: 241196
2015-07-01 21:57:51 +00:00
Dan Gohman d82494bb75 [WebAssembly] Define separate Target instances for 32-bit and 64-bit.
llvm-svn: 241193
2015-07-01 21:42:34 +00:00
Jingyue Wu a0a56601c0 [NVPTX] expand extload/truncstore for vectors of floats
Summary:
According to PTX ISA:

For convenience, ld, st, and cvt instructions permit source and destination data operands to be wider than the instruction-type size, so that narrow values may be loaded, stored, and converted using regular-width registers. For example, 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded, stored, or converted to other types and sizes. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types; floating-point instruction types still require that the operand type-size matches exactly, unless the operand is of bit-size type.

So, the ISA does not support load with extending/store with truncatation for floating numbers. This is reflected in setting the loadext/truncstore actions to expand in the code for floating numbers, but vectors of floating numbers are not taken care of.

As a result, loading a vector of floats followed by a fp_extend may be combined by DAGCombiner to a extload, and the extload may be lowered to NVPTXISD::LoadV2 with extending information. However, NVPTXISD::LoadV2 does not perform extending, and no extending instructions are inserted. Finally, PTX instructions with mismatched types are generated, like
ld.v2.f32 {%fd3, %fd4}, [%rd2]

This patch adds the correct actions for vectors of floats, so DAGCombiner would not create loads with extending, and correct code is generated.

Patched by Gang Hu. 

Test Plan: Test case attached.

Reviewers: jingyue

Reviewed By: jingyue

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D10876

llvm-svn: 241191
2015-07-01 21:32:42 +00:00