05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
748265b0da
Simplify test and move into a generic "crash" ll file.
...
llvm-svn: 116130
2010-10-09 00:29:04 +00:00
59ebe44049
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
af8b4871a8
Call InitSections in llc and clang so that the binaries produced by them
...
are easier to diff with those produced by llvm-mc.
llvm-svn: 116095
2010-10-08 19:37:38 +00:00
d57f9ecd4a
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
cf97db2402
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
a07b5c291d
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
056b694de1
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
3e210eb398
testcase that goes with r116053
...
llvm-svn: 116054
2010-10-08 05:12:30 +00:00
8ed76f87cf
rename test
...
llvm-svn: 116052
2010-10-08 05:05:06 +00:00
420cf26d99
merge tests
...
llvm-svn: 116051
2010-10-08 05:04:58 +00:00
6a8a65cb43
filecheckize.
...
llvm-svn: 116050
2010-10-08 05:02:29 +00:00
dd77477690
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
00ee155b25
Fix Formatting.
...
llvm-svn: 116038
2010-10-08 03:17:21 +00:00
8eb636e5de
MC-COFF: Fix Simple and Complex type. Fixes PR8320.
...
llvm-svn: 116037
2010-10-08 03:17:11 +00:00
efdf08b5b8
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
134f415bf8
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
42a07e8545
Add test file for simple ARM binary encodings with MC
...
llvm-svn: 116024
2010-10-08 00:47:59 +00:00
00be34d009
MC-COFF: Add test for my last commit.
...
llvm-svn: 116015
2010-10-08 00:00:28 +00:00
57da4caa85
Remove LoopIndexSplit pass. It is neither maintained nor used by anyone.
...
llvm-svn: 116004
2010-10-07 23:29:37 +00:00
ae8d67d3bb
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
5c31bf0619
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
1666b61357
MC-COFF: Fix symbol aliases. Fixes PR8251.
...
llvm-svn: 115909
2010-10-07 06:29:33 +00:00
efc22274cd
test: Fix binary stdin issues with coff-dump on Windows.
...
llvm-svn: 115908
2010-10-07 06:29:21 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
5f2d6a5cd9
Get binding and visibility info from the the alias, but Type from the symbol
...
being aliased.
llvm-svn: 115836
2010-10-06 21:02:29 +00:00
d444577382
If a symbol is global, reloc against it even if it is in a mergeable section.
...
llvm-svn: 115817
2010-10-06 19:27:21 +00:00
83b2a3337f
Make sure weak symbols are listed after the local ones.
...
llvm-svn: 115795
2010-10-06 16:47:31 +00:00
8f3d2c9058
Correctly handle GOTPCREL relocations.
...
llvm-svn: 115793
2010-10-06 16:23:36 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
28f034c21a
Generalize tblgen's dag parsing logic to handle arbitrary expressions
...
as the operator of the dag. Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).
Unfortunately, this runs afoul of an idiom being used by llvmc. It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo. With this change, this is parsed as a [1,2,3]
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.
llvm-svn: 115742
2010-10-06 04:55:48 +00:00
805b74d650
rename add some comments.
...
llvm-svn: 115741
2010-10-06 04:37:17 +00:00
7d5bb96723
filecheckize
...
llvm-svn: 115740
2010-10-06 04:36:30 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
d7565c3a06
Use a relocation against the symbol if it is a PLT and the symbol is in another
...
section. Common because of linkonce sections.
llvm-svn: 115718
2010-10-05 23:57:26 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
...
simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
0ad137e98e
Implement more alias cases.
...
llvm-svn: 115699
2010-10-05 22:26:43 +00:00
10a0fdeab5
PSHUFW is in SSE, not SSSE3.
...
llvm-svn: 115691
2010-10-05 21:58:12 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
c58a37ea51
Don't crash in a strange .size directive.
...
llvm-svn: 115684
2010-10-05 21:02:45 +00:00
a3b34ed2df
MC-COFF: Fix (PR8278) temporary symbol relocations.
...
llvm-svn: 115656
2010-10-05 19:48:03 +00:00
b91bac6c96
Add support for a fill value in the .zero directive.
...
llvm-svn: 115655
2010-10-05 19:42:57 +00:00
b1d0789357
Implement a simple alias case and refactor the code a bit so that the
...
isInSymtab and isLocal logic in the two loops don't get easily out of sync.
llvm-svn: 115643
2010-10-05 18:01:23 +00:00
8ccdd25fbd
test/COFF: Fix symbol indexes and names. Update tests to match.
...
llvm-svn: 115642
2010-10-05 17:57:08 +00:00
f6230d1d4b
test/COFF: Remove temp file usage.
...
llvm-svn: 115641
2010-10-05 17:56:56 +00:00
e58f37f74d
test/coff-dump: Support reading from stdin.
...
llvm-svn: 115640
2010-10-05 17:56:46 +00:00
868aaf3c3d
Cleanup Whitespace.
...
llvm-svn: 115639
2010-10-05 17:56:37 +00:00
d8d1dcc09a
Use a more efficient lowering of uint64_t --> float that can take advantage of hardware signed integer conversion without
...
having to do a double cast (uint64_t --> double --> float). This is based on the algorithm from compiler_rt's __floatundisf
for X86-64.
llvm-svn: 115634
2010-10-05 17:24:05 +00:00
d03e81dba8
Produce a undefined reference to _GLOBAL_OFFSET_TABLE_ when needed.
...
llvm-svn: 115623
2010-10-05 15:48:37 +00:00
259bcdad06
Tests that now pass.
...
llvm-svn: 115622
2010-10-05 15:43:32 +00:00
7681b41720
test/CodeGen/X86/atomic_op.ll: Rename @main to @func. Extra sequences will be inserted to @main as prologue on cygming, to fail.
...
llvm-svn: 115611
2010-10-05 11:16:24 +00:00
6296bbbb65
Added a testcase for the ENTER instruction.
...
llvm-svn: 115580
2010-10-05 00:21:40 +00:00
402e54822b
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
...
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
llvm-svn: 115552
2010-10-04 20:24:01 +00:00
fd1fff8b19
Implement ELF::R_X86_64_GOTPCREL.
...
llvm-svn: 115547
2010-10-04 19:51:39 +00:00
baadbd554a
Produce a R_X86_64_PLT32 when needed.
...
llvm-svn: 115541
2010-10-04 19:04:13 +00:00
b2c4ca6433
Produce a R_X86_64_GOT32 when needed.
...
llvm-svn: 115537
2010-10-04 18:44:25 +00:00
87f77b5f9a
Add hook in MCSection to decide when to use "optimized nops", for each
...
section kind. Previously, optimized nops were only used for MachO.
Also added tests for ELF and COFF.
llvm-svn: 115523
2010-10-04 17:32:41 +00:00
da0e3d07b2
Include the section address in the computation of the relocation.
...
llvm-svn: 115509
2010-10-04 15:59:01 +00:00
7c48b06930
Correctly compute the relocation when it is not in the first fragment.
...
llvm-svn: 115506
2010-10-04 15:28:43 +00:00
d77a443631
va_args support for Win64.
...
Patch by Cameron!
llvm-svn: 115480
2010-10-03 22:52:07 +00:00
ff85688559
Properly emit stack probe on win64 (for non-mingw targets).
...
Based on the patch by Cameron Esfahani!
llvm-svn: 115479
2010-10-03 22:02:38 +00:00
bb48e26732
Add 3DNowA instructions.
...
llvm-svn: 115477
2010-10-03 20:23:13 +00:00
f909b07340
unbreak buildbot
...
llvm-svn: 115476
2010-10-03 20:02:48 +00:00
d3593c3a8e
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
...
llvm-svn: 115473
2010-10-03 19:09:13 +00:00
b44b202d66
add support for the prefetch/prefetchw instructions, move femms into
...
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
llvm-svn: 115468
2010-10-03 18:42:30 +00:00
3a0a620c2e
what the heck, add support for the rest of the 3dNow! binary operations.
...
llvm-svn: 115467
2010-10-03 18:24:18 +00:00
45270db916
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
5d9089ae14
Add test to make sure that the MMX intrinsic calls make it out the other end in
...
tact.
llvm-svn: 115458
2010-10-03 03:30:30 +00:00
14d07adf0b
Auto-upgrade tests for the new MMX intrinsic calls.
...
llvm-svn: 115456
2010-10-03 01:12:20 +00:00
f70b4e0c2e
Implement a very basic PIC case.
...
llvm-svn: 115454
2010-10-03 00:46:57 +00:00
4756bbeba0
fix a regression introduced in r115243, in which the instruction
...
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
llvm-svn: 115422
2010-10-02 21:32:15 +00:00
a2f2c27b20
actually, move the elf tests into the existing elf dir.
...
llvm-svn: 115416
2010-10-02 18:53:48 +00:00
7b1638b40b
consolidate ELF tests into asmparser tests.
...
llvm-svn: 115415
2010-10-02 18:52:57 +00:00
fbae9435c9
move ARM MC tests up one level.
...
llvm-svn: 115414
2010-10-02 18:52:05 +00:00
bf73fe5e8d
Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else.
...
llvm-svn: 115352
2010-10-01 21:39:35 +00:00
13a642da0b
Now that the profitable bits of EnableFullLoadPRE have been enabled by default, rip out the remainder.
...
Anyone interested in more general PRE would be better served by implementing it separately, to get real
anticipation calculation, etc.
llvm-svn: 115337
2010-10-01 20:02:55 +00:00
d3fe5fa5d1
Fix code gen crash reported in PR 8235. We still lose debug info for the unused argument here. This is a known limitation recorded debuginfo-tests/trunk/dbg-declare2.ll function 'f6' test case.
...
llvm-svn: 115323
2010-10-01 19:00:44 +00:00
a39904e6b9
We must check for something.
...
llvm-svn: 115309
2010-10-01 10:20:10 +00:00
0e5e4b7b76
Disable tests until I can figure out why they're failing on just two machines but not others.
...
llvm-svn: 115308
2010-10-01 10:01:10 +00:00
b3a1022572
Try adding an mtriple.
...
llvm-svn: 115307
2010-10-01 09:40:50 +00:00
56f7cd255b
Zap some redundant 'ori $?, $?, 0' from SPU.
...
Also remove some code that died in the process.
One now non-existant ori is checked for.
llvm-svn: 115306
2010-10-01 09:20:01 +00:00
3b2b1e7942
FileCheck-ize this test.
...
llvm-svn: 115304
2010-10-01 08:55:48 +00:00
9b6853c6eb
FileCheck-ize this test.
...
llvm-svn: 115303
2010-10-01 08:50:12 +00:00
c663a67384
fix PR8267 - Instcombine shouldn't optimizer away volatile memcpy's.
...
llvm-svn: 115296
2010-10-01 05:51:02 +00:00
98e82678bd
upgrade this test.
...
llvm-svn: 115295
2010-10-01 05:47:16 +00:00
a205055857
fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350
...
llvm-svn: 115294
2010-10-01 05:36:09 +00:00
f419de0852
One more +sse2.
...
llvm-svn: 115293
2010-10-01 05:08:18 +00:00
4ca7bb52d0
move X86 subdir up a level
...
llvm-svn: 115292
2010-10-01 04:32:20 +00:00
bb6b961867
Mark all these as needing SSE2. Should fix PPC and
...
maybe even Linux.
llvm-svn: 115291
2010-10-01 04:17:55 +00:00
ab60ae3cf3
Disable these tests for now; it's not obvious why they fail on Linux.
...
llvm-svn: 115257
2010-10-01 00:59:21 +00:00
c6f17f7420
Make test not sensitive to register choice.
...
llvm-svn: 115250
2010-10-01 00:16:17 +00:00
dd224d2333
Massive rewrite of MMX:
...
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
bb995ae261
test/CodeGen/X86/sibcall.ll: Add explicit triplets and remove XFAIL: apple-darwin8.
...
llvm-svn: 115215
2010-09-30 22:02:06 +00:00
3170a25a84
We do want to allow LoadPRE to perform LICM-like transformations: we already consider PHI nodes to be negligible for
...
code size (making this transform code size neutral), and it allows us to hoist values out of loops, which is always
a good thing.
llvm-svn: 115205
2010-09-30 20:53:04 +00:00
eb12f49fb7
Try again to disable critical edge splitting in CodeGenPrepare.
...
The bug that broke i386 linux has been fixed in r115191.
llvm-svn: 115204
2010-09-30 20:51:52 +00:00
f987d5ea1c
Factor some logic into ShouldRelocOnSymbol. This simplifies the code and
...
fixes some cases where we were producing relocations with at symbol that
should use a section instead.
llvm-svn: 115194
2010-09-30 20:18:35 +00:00
665aa6efcc
When isel is emitting instructions for an x86 target without CMOV, the CFG is
...
edited during emission.
If the basic block ends in a switch that gets lowered to a jump table, any
phis at the default edge were getting updated wrong. The jump table data
structure keeps a pointer to the header blocks that wasn't getting updated
after the MBB is split.
This bug was exposed on 32-bit Linux when disabling critical edge splitting in
codegen prepare.
The fix is to uipdate stale MBB pointers whenever a block is split during
emission.
llvm-svn: 115191
2010-09-30 19:44:31 +00:00
1dee57fb7d
more cleanups.
...
llvm-svn: 115178
2010-09-30 17:29:05 +00:00
288a5f9652
merge and clean up tests.
...
llvm-svn: 115177
2010-09-30 17:24:05 +00:00
60217e765e
merge two tests.
...
llvm-svn: 115175
2010-09-30 17:18:22 +00:00
41a0cd14b7
rename test
...
llvm-svn: 115174
2010-09-30 17:16:49 +00:00
ea226b24ff
generalize test.
...
llvm-svn: 115172
2010-09-30 17:15:42 +00:00
28307d1a1e
rename test.
...
llvm-svn: 115171
2010-09-30 17:14:55 +00:00
45a52f3c34
merge two tests.
...
llvm-svn: 115170
2010-09-30 17:14:30 +00:00
73a7caee4b
preemptively add the rest of the non-n fpstack instructions.
...
llvm-svn: 115168
2010-09-30 17:11:29 +00:00
28b3b43fb4
merge two tests.
...
llvm-svn: 115165
2010-09-30 17:05:37 +00:00
1e9e49f421
fix this to not be completely broken.
...
llvm-svn: 115164
2010-09-30 17:04:59 +00:00
c8f0e29b5e
update, unxfail, fix bogus encodings.
...
llvm-svn: 115163
2010-09-30 17:03:20 +00:00
a9e913e139
update and unxfail
...
llvm-svn: 115162
2010-09-30 17:00:53 +00:00
ccf2c765f0
unxfail this by fixing syntactic differences.
...
llvm-svn: 115161
2010-09-30 16:59:28 +00:00
4373badcdf
implement support for finit, PR8258
...
llvm-svn: 115156
2010-09-30 16:42:53 +00:00
adc0dbe470
add support for fstcw, PR8259
...
llvm-svn: 115154
2010-09-30 16:39:29 +00:00
efbdbe5565
Move logic of determining ELF entsize from the .s printer to initialization
...
time. That way, the EntrySize field is initialized for other code paths,
namely, the .ll -> .o code path.
llvm-svn: 115141
2010-09-30 05:59:22 +00:00
9d98ac645e
Add another test that now passes.
...
llvm-svn: 115137
2010-09-30 04:22:07 +00:00
70d6e0e0ff
Correctly produce R_X86_64_32 or R_X86_64_32S.
...
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
2010-09-30 03:11:42 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
...
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
b96b2d8e4d
Have ELFAsmParser.cpp use the already parsed "Size" (entry size) when
...
constructing a section. Test for a few cases also included.
llvm-svn: 115132
2010-09-30 02:41:46 +00:00
2ebaee9c75
Make it possible for the MCObjectWriter to decide if a given fixup is fully
...
resolved or not. Different object files have different restrictions and
different native assemblers have different idiosyncrasies we want to emulate
for now.
Move the existing MachO logic to the new place and implement an ELF one that
gets fixups to globals right.
llvm-svn: 115131
2010-09-30 02:22:20 +00:00
2b76c66fd6
Add constant folding for strspn and strcspn to SimplifyLibCalls.
...
llvm-svn: 115116
2010-09-30 00:58:35 +00:00
38d22f69fc
Add strpbrk folding to SimplifyLibCalls.
...
llvm-svn: 115111
2010-09-29 23:52:12 +00:00
8e861d7eee
Simplify the loop in StrChrOptimizer. FileCheckize test.
...
llvm-svn: 115095
2010-09-29 22:29:12 +00:00
824645abc9
Teach SimplifyLibCalls how to optimize strrchr.
...
llvm-svn: 115091
2010-09-29 21:50:51 +00:00
95ae73c394
Generalize DISubprogram element to encode various flags instead of just one boolean for isArtificial.
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This is a backword compatible change.
llvm-svn: 115084
2010-09-29 21:04:46 +00:00
99c985c37d
Fix PR8247: JumpThreading can cause a block to become unreachable while still having predecessor, if it is part of a self-loop.
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Because of this, we cannot use the Simplify* APIs, as they can assert-fail on unreachable code. Since it's not easy to determine
if a given threading will cause a block to become unreachable, simply defer simplifying simplification to later InstCombine and/or
DCE passes.
llvm-svn: 115082
2010-09-29 20:34:41 +00:00
0aea752f6d
Remove PointerTracking tests.
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llvm-svn: 115072
2010-09-29 19:20:35 +00:00
2b43c1cf42
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
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llvm-svn: 115061
2010-09-29 18:39:16 +00:00
97bf273870
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
2010-09-29 17:54:10 +00:00
53f0bf194a
Move "local commons" to the end of .bss to match the gnu as behavior.
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llvm-svn: 115037
2010-09-29 14:52:01 +00:00
68e05d404a
Add a test that I forgot to add with a previous commit.
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llvm-svn: 115036
2010-09-29 14:40:49 +00:00
c2eb72dc2a
do not compare actual branch labels; this may fix llvm-gcc-x86_64-darwin10-cross-mingw32 buildbot too
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llvm-svn: 115034
2010-09-29 10:45:43 +00:00
d36e3e8850
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
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added some doxygen on the way
llvm-svn: 115033
2010-09-29 10:12:08 +00:00
8f7851d2b4
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
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llvm-svn: 115029
2010-09-29 05:05:03 +00:00
52e6020883
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
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llvm-svn: 115027
2010-09-29 04:55:40 +00:00
822dc48c3a
MC-COFF: Fix test. IMAGE_SYM_CLASS_LABEL should never have been emitted.
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llvm-svn: 115024
2010-09-29 03:59:25 +00:00
5da7f9fcfd
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
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order as cctools for diffability.
llvm-svn: 115022
2010-09-29 03:43:43 +00:00
a4e1c74947
implement support for 32-bit address operands in 64-bit mode, which
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are defined to emit the 0x67 prefix byte. rdar://8482675
llvm-svn: 115021
2010-09-29 03:33:25 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
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operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
ff3a3930a0
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
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Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
llvm-svn: 115018
2010-09-29 02:36:32 +00:00
ef1c2fc305
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
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llvm-svn: 115017
2010-09-29 02:24:57 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
cc91601211
And remove r114997's test.
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llvm-svn: 115003
2010-09-28 23:24:18 +00:00
b0b2c57149
Revert r114997. It was causing a failure on darwin10-selfhost.
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llvm-svn: 115002
2010-09-28 23:11:55 +00:00
d848beb1e5
Fix a FIXME. _foo.eh symbols are currently always exported so that the linker
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knows about them. This is not necessary on 10.6 and later.
llvm-svn: 114997
2010-09-28 22:36:56 +00:00
a3181e2d79
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
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cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
llvm-svn: 114995
2010-09-28 21:57:50 +00:00
81bdc93bbb
User proper libcall names & condcodes while compiling for ARM EABI.
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Patch by Evzen Muller!
llvm-svn: 114991
2010-09-28 21:39:26 +00:00
88af7d00fc
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
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Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
llvm-svn: 114973
2010-09-28 18:32:13 +00:00
0ab27ea44f
Add target triple info to these tests to make the results comparable when
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hosted on different platforms.
llvm-svn: 114965
2010-09-28 17:10:36 +00:00
01d20a76fe
On elf, undefined symbols can start with .L.
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llvm-svn: 114958
2010-09-28 16:19:11 +00:00
3dc97324c1
Add a command line option "-arm-strict-align" to disallow unaligned memory
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accesses for ARM targets that would otherwise allow it. Radar 8465431.
llvm-svn: 114941
2010-09-28 04:09:35 +00:00
Evan Cheng