Commit Graph

5760 Commits

Author SHA1 Message Date
Simon Dardis da96c43682 [MIPS] Handle PIC load address macro instructions in N64.
In particular, use CALL16 (similar to O32) for address loads into T9 for certain
cases.  Otherwise use a %got_disp relocation to load the address of a symbol.
Small offsets (small enough to fit in a 16-bit signed immediate) can be used and
are added to the symbol address after it is loaded from the GOT.  Larger offsets
are currently unsupported and result in an error from the assembler.

Reviewers: sdardis

Reviewed By: sdardis

Patch by: John Baldwin

Subscribers: llvm-commits, seanbruno, arichardson, emaste, dim

Differential Revision: https://reviews.llvm.org/D33948

llvm-svn: 306831
2017-06-30 15:44:27 +00:00
Ulrich Weigand 9932f92882 [SystemZ] Add missing high-word facility instructions
There are a few instructions provided by the high-word facility (z196)
that we cannot easily exploit for code generation.  This patch at least
adds those missing instructions for the assembler and disassembler.

This means that now all nonprivileged instructions up to z13 are
supported by the LLVM assembler / disassembler.

llvm-svn: 306821
2017-06-30 12:56:29 +00:00
Rafael Espindola 96367a3d1e Fix PR33625.
We were failing to convert this expression to pcrel.

llvm-svn: 306573
2017-06-28 17:56:07 +00:00
Mandeep Singh Grang 0c72172e32 [COFF, ARM64] Add support for Windows ARM64 COFF format
Summary:
This is the llvm part of the initial implementation to support Windows ARM64 COFF format.
I will gradually add more functionality in subsequent patches.

Reviewers: ruiu, rnk, t.p.northover, compnerd

Reviewed By: ruiu, compnerd

Subscribers: aemerson, mgorny, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D34705

llvm-svn: 306490
2017-06-27 23:58:19 +00:00
Sam Clegg 9e1ade93a8 [WebAssembly] Add data size and alignement to linking section
The overal size of the data section (including BSS)
is otherwise not included in the wasm binary.

Differential Revision: https://reviews.llvm.org/D34657

llvm-svn: 306459
2017-06-27 20:27:59 +00:00
Coby Tayree 41a5b55f50 [X86][AsmParser][MS-compatability] Binary/Unary operators enhancements
Introducing MOD binary operator
https://msdn.microsoft.com/en-us/library/hha180wt.aspx

Enhancing unary operators NEG and NOT, to support more complex patterns

Differential Revision: https://reviews.llvm.org/D33876

llvm-svn: 306425
2017-06-27 16:58:27 +00:00
Simon Dardis 4155c8f1f3 [mips] Add instruction aliases for ds(r|l)l.
Add the instruction aliases for ds(r|l)l for the two operand alias
of ds(r|l)lv and the aliases ds(r|l)l with the three register operands.

llvm-svn: 306405
2017-06-27 13:35:17 +00:00
Sam Clegg 933df2658d [WebAssembly] Add more support for weak symbols
Add weak symbol tests to MC
Add symbol flags to output of `llvm-readobj -t`.

Differential Revision: https://reviews.llvm.org/D34635

llvm-svn: 306330
2017-06-26 21:01:39 +00:00
Hiroshi Inoue 4484ff03df fix trivial typo in comment, NFC
llvm-svn: 306274
2017-06-26 06:32:04 +00:00
Rafael Espindola 801b42de31 ARM: move some logic from processFixupValue to applyFixup.
processFixupValue is called on every relaxation iteration. applyFixup
is only called once at the very end. applyFixup is then the correct
place to do last minute changes and value checks.

While here, do proper range checks again for fixup_arm_thumb_bl. We
used to do it, but dropped because of thumb2. We now do it again, but
use the thumb2 range.

llvm-svn: 306177
2017-06-23 22:52:36 +00:00
Petar Jovanovic 53dbfb3798 Reland r306095: [mips] Fix reg positions in the aui/daui instructions
After fixing (r306173) a failing test in the lld test suite (r306173),
reland r306095.

Original commit message:

  [mips] Fix register positions in the aui/daui instructions

  Swapped the position of the rt and rs register in the aui/daui
  instructions for mips32r6 and mips64r6. With this change, the format of
  the generated instructions complies with specifications and GCC.
  Patch by Milos Stojanovic.

llvm-svn: 306174
2017-06-23 22:37:19 +00:00
Petar Jovanovic 78811c2c07 Revert r306095: [mips] Fix reg positions in the aui/daui instructions
ELF/mips-plt-r6.s in lld-test is failing. Reverting the change.

Original commit message:

  [mips] Fix register positions in the aui/daui instructions

  Swapped the position of the rt and rs register in the aut/daui
  instructions for mips32r6 and mips64r6. With this change, the format of
  the generated instructions complies with specifications and GCC.
  Patch by Milos Stojanovic.

llvm-svn: 306099
2017-06-23 13:33:46 +00:00
Petar Jovanovic d5f7711ebb [mips] Fix register positions in the aui/daui instructions
Swapped the position of the rt and rs register in the aut/daui instructions
for mips32r6 and mips64r6. With this change, the format of the generated
instructions complies with specifications and GCC.

Patch by Milos Stojanovic.

Differential Revision: https://reviews.llvm.org/D33988

llvm-svn: 306095
2017-06-23 12:47:18 +00:00
Rafael Espindola 58173b9720 COFF: Produce an error on invalid pcrel relocs.
X86_64 COFF only has support for 32 bit pcrel relocations. Produce an
error on all others.

Note that gnu as has extended the relocation values to support
this. It is not clear if we should support the gnu extension.

llvm-svn: 306082
2017-06-23 04:07:44 +00:00
Rafael Espindola 13811b0605 Make the test a bit more strict. NFC.
llvm-svn: 306080
2017-06-23 03:48:01 +00:00
Rafael Espindola 34e94a8783 COFF: handle "undef - ." expressions.
This is another thing that the ELF implementation can do but is
missing from COFF.

llvm-svn: 306078
2017-06-23 02:15:56 +00:00
Rafael Espindola d2edd137df Change creation of relative relocations on COFF.
For whatever reason, when processing

  .globl foo
foo:
  .data
bar:
  .long foo-bar

llvm-mc creates a relocation with the section:

0x0 IMAGE_REL_I386_REL32 .text

This is different than when the relocation is relative from the
beginning. For example, a file with

call foo

produces

0x0 IMAGE_REL_I386_REL32 foo

I would like to refactor the logic for converting "foo - ." into a
relative relocation so that it is shared with ELF. This is the first
step and just changes the coff implementation to match what ELF (and
COFF in the case of calls) does.

llvm-svn: 306063
2017-06-22 21:57:04 +00:00
Reid Kleckner 40a47a8702 [MC] Allow assembling .secidx and .secrel32 for undefined symbols
There's nothing incorrect about emitting such relocations against
symbols defined in other objects. The code in EmitCOFFSec* was missing
the visitUsedExpr part of MCStreamer::EmitValueImpl, so these symbols
were not being registered with the object file assembler.

This will be used to make reduced test cases for LLD.

llvm-svn: 306057
2017-06-22 21:02:14 +00:00
Rafael Espindola 8a261c2565 Add a common error checking for some invalid expressions.
This refactors a bit of duplicated code and fixes an assertion failure
on ELF.

llvm-svn: 306035
2017-06-22 17:25:35 +00:00
David Stuttard 70e8bc1bf3 [AMDGPU] Add intrinsics for tbuffer load and store
Intrinsic already existed for llvm.SI.tbuffer.store

Needed tbuffer.load and also re-implementing the intrinsic as llvm.amdgcn.tbuffer.*

Added CodeGen tests for the 2 new variants added.
Left the original llvm.SI.tbuffer.store implementation to avoid issues with existing code

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr

Differential Revision: https://reviews.llvm.org/D30687

llvm-svn: 306031
2017-06-22 16:29:22 +00:00
Krzysztof Parzyszek f63ad39e7d [Hexagon] Handle a global operand to A2_addi when creating duplexes
llvm-svn: 306012
2017-06-22 15:53:31 +00:00
Florian Hahn 5991b5be74 [ARM] Create relocations for beq.w branches to ARM function syms.
Summary:
The ARM ELF ABI requires the linker to do interworking for wide
conditional branches from Thumb code to ARM code. 

That was pointed out by @peter.smith in the comments for D33436.

Reviewers: rafael, peter.smith, echristo

Reviewed By: peter.smith

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, peter.smith

Differential Revision: https://reviews.llvm.org/D34447

llvm-svn: 306009
2017-06-22 15:32:41 +00:00
Petar Jovanovic 636851b845 [mips] Allow $AT to be used as a register name
This patch allows $AT to be used as a register name in assembly files.
Currently only $at is recognized as a valid register name.

Patch by Stanislav Ocovaj.

Differential Revision: https://reviews.llvm.org/D34348

llvm-svn: 306007
2017-06-22 15:24:16 +00:00
Simon Dardis 1c73fcc131 [mips] Implement the ".rdata" MIPS assembly directive.
Rather than creating a separate ".rdata" section distinct from the
customary ".rodata" in ELF, ".rdata" switches to the ".rodata" section.

This patch relands r305949 and r305950 with the correct commit message
and addresses nit raised during review.

Patch By: John Baldwin!

Differential Revision: https://reviews.llvm.org/D34452

llvm-svn: 305995
2017-06-22 10:41:51 +00:00
John Brawn ed78aaf093 [ARM] Add .w aliases of MOV with shifted operand
These appear to have been simply missing.

Differential Revision: https://reviews.llvm.org/D34461

llvm-svn: 305993
2017-06-22 10:30:53 +00:00
Rafael Espindola f9df429068 Also test thumb.
llvm-svn: 305976
2017-06-22 00:44:05 +00:00
Dmitry Preobrazhensky 851a3d9f05 [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failures
See Bug 33509: https://bugs.llvm.org//show_bug.cgi?id=33509

Reviewers: Sam Kolton, Artem Tamazov, Valery Pykhtin

Differential Revision: https://reviews.llvm.org/D34360

llvm-svn: 305923
2017-06-21 16:00:54 +00:00
Dmitry Preobrazhensky dc4ac823ec [AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is different than any of the src
See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D34003

llvm-svn: 305915
2017-06-21 14:41:34 +00:00
Rafael Espindola 2c8e3ed00f Simplify test.
llvm-svn: 305881
2017-06-21 06:42:56 +00:00
Rafael Espindola 5f4a10bf23 Make this test a bit more strict. NFC.
llvm-svn: 305855
2017-06-20 21:11:58 +00:00
Matt Arsenault 9698f1c862 AMDGPU: Start adding global_* instructions
llvm-svn: 305838
2017-06-20 19:54:14 +00:00
Artem Tamazov 314eafb73d [AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests.
A new Gfx9 dasm test added with approx 29000 cases.
Existing tests extended by (approx.):
* Gfx7 asm: 5000 test cases
* Gfx8 asm: 5000 test cases
* Gfx9 asm: 14400 test cases
* Gfx8 dasm: 5200 test cases

llvm-svn: 305702
2017-06-19 15:55:02 +00:00
Sam Clegg 9d24fb7ff3 [WebAssembly] Use __stack_pointer global when writing wasm binary
This ensures that symbolic relocations are generated for stack
pointer manipulations.

These relocations are of type R_WEBASSEMBLY_GLOBAL_INDEX_LEB.
This change also adds support for reading relocations of this
type in WasmObjectFile.cpp.

Since its a globally imported symbol this does mean that
the get_global/set_global instruction won't be valid until
the objects are linked that global used in no longer an
imported global.

Differential Revision: https://reviews.llvm.org/D34172

llvm-svn: 305616
2017-06-16 23:59:10 +00:00
Peter Collingbourne f0e26e7270 MC, Object: Reserve a section type, SHT_LLVM_ODRTAB, for the ODR table.
This is part of the ODR checker proposal:
http://lists.llvm.org/pipermail/llvm-dev/2017-June/113820.html

Per discussion on the gnu-gabi mailing list [1] the section type range
0x6fff4c00..0x6fff4cff is reserved for LLVM.

[1] https://sourceware.org/ml/gnu-gabi/2017-q2/msg00030.html

Differential Revision: https://reviews.llvm.org/D33978

llvm-svn: 305407
2017-06-14 18:52:12 +00:00
Sam Clegg 7736855dee [WebAssembly] Fix symbol type for addresses of external functions
These symbols were previously not being marked as functions
so were appearing as globals instead, and with the incorrect
relocation type.

Without this fix, objects that take address of external
functions include them as global imports rather than function
imports which then fails at link time.

Differential Revision: https://reviews.llvm.org/D34068

llvm-svn: 305263
2017-06-13 01:42:21 +00:00
Sam Clegg d99f6078e4 [WebAssembly] MC: Fix value of R_WEBASSEMBLY_TABLE_INDEX relocations
Previously we were writing the value function index space
value but for these types of relocations we want to be
writing the table element index space value.

Add a test case for these relocation types that fails
without this change.

Differential Revision: https://reviews.llvm.org/D33962

llvm-svn: 305253
2017-06-12 23:52:44 +00:00
Peter Collingbourne 89061b2224 IR: Replace the "Linker Options" module flag with "llvm.linker.options" named metadata.
The new metadata is easier to manipulate than module flags.

Differential Revision: https://reviews.llvm.org/D31349

llvm-svn: 305227
2017-06-12 20:10:48 +00:00
Tony Jiang 30a49d1a3d [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.
Note that if we need the result of both the divide and the modulo then we
compute the modulo based on the result of the divide and not using the new
hardware instruction.

Commit on behalf of STEFAN PINTILIE.
Differential Revision: https://reviews.llvm.org/D33940

llvm-svn: 305210
2017-06-12 17:58:42 +00:00
Matt Arsenault fd02314113 AMDGPU: Start adding offset fields to flat instructions
llvm-svn: 305194
2017-06-12 15:55:58 +00:00
Wei Ding 7c3e5115a5 AMDGPU : Fix ISA Version Definitions.
Differential Revision: http://reviews.llvm.org/D28531

llvm-svn: 305137
2017-06-10 03:53:19 +00:00
Nirav Dave 670109d89a [MC] Fix compiler crash in AsmParser::Lex
When an empty comment is present in an assembly file, the compiler will crash because it checks the first character for '\n' or '\r'.
The fix consists of also checking if the string is empty before accessing the *front* method of the StringRef.
A test is included for the x86 target, but this issue is reproducible with other targets as well.

Patch by Alexandru Guduleasa!

Reviewers: niravd, grosbach, llvm-commits

Reviewed By: niravd

Differential Revision: https://reviews.llvm.org/D33993

llvm-svn: 305077
2017-06-09 14:04:03 +00:00
Evgeniy Stepanov 60d411b66e [MachO] Fix codegen of alias of alias.
Fixes PR33316.

llvm-svn: 305012
2017-06-08 20:49:03 +00:00
Dmitry Preobrazhensky 5a2f881b39 [AMDGPU][MC] Corrected error message for s_waitcnt helpers
See Bug 32711: https://bugs.llvm.org//show_bug.cgi?id=32711

Reviewers: artem.tamazov

Differential Revision: https://reviews.llvm.org/D33781

llvm-svn: 304922
2017-06-07 16:08:02 +00:00
Petar Jovanovic 2f5f8e947a [mips][dsp] Modify repl.ph to accept signed immediate values
Changed immediate type for repl.ph from uimm10 to simm10 as per the specs.
Repl.qb still accepts uimm8. Both instructions now mimic the behaviour of
GNU as.

Patch by Stefan Maksimovic.

Differential Revision: https://reviews.llvm.org/D33594

llvm-svn: 304918
2017-06-07 14:48:46 +00:00
Florian Hahn 9afd9d9254 [ARM] Create relocations for unconditional branches.
Summary:
Relocations are required for unconditional branches to function symbols with
different execution mode. Without this patch, incorrect branches are
generated for tail calls between functions with different execution
mode.


Reviewers: peter.smith, rafael, echristo, kristof.beyls

Reviewed By: peter.smith

Subscribers: aemerson, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33898

llvm-svn: 304882
2017-06-07 08:54:47 +00:00
Sam Clegg acd7d2b00b [WebAssembly] MC: Refactor relocation handling
The change cleans up and unifies the handling of relocation
entries in WasmObjectWriter.  Type index relocation no longer
need to be handled separately.

The only externally visible change should be that type
index relocations are no longer grouped at the end.

Differential Revision: https://reviews.llvm.org/D33918

llvm-svn: 304816
2017-06-06 19:15:05 +00:00
Javed Absar ba94c7bde1 Move ARM specific test to ELF/ARM dir
Moving ARM specific test clang-section.s
from MC/ELF to MC/ELF/ARM
Buildbots reported failures on
commit  https://reviews.llvm.org/rL304705
Full details are available at:
 http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/10333

llvm-svn: 304706
2017-06-05 10:53:26 +00:00
Javed Absar b16d146838 Add support for #pragma clang section
This patch provides a means to specify section-names for global variables,
functions and static variables, using #pragma directives.
This feature is only defined to work sensibly for ELF targets.
One can specify section names as:
#pragma clang section bss="myBSS" data="myData" rodata="myRodata" text="myText"
One can "unspecify" a section name with empty string e.g.
#pragma clang section bss="" data="" text="" rodata=""

Reviewers: Roger Ferrer, Jonathan Roelofs, Reid Kleckner
Differential Revision: https://reviews.llvm.org/D33413

llvm-svn: 304704
2017-06-05 10:09:13 +00:00
Peter Smith adde667007 [ARM] Support fixup for Thumb2 modified immediate
This change adds a new fixup fixup_t2_so_imm for the t2_so_imm_asmoperand
"T2SOImm". The fixup permits code such as:
.L1:
 sub r3, r3, #.L2 - .L1
.L2:
to assemble in Thumb2 as well as in ARM state.
    
The operand predicate isT2SOImm() explicitly doesn't match expressions
containing :upper16: and :lower16: as expressions with these operators
must match the movt and movw instructions.
    
The test mov r0, foo2 in thumb2-diagnostics is moved to a new file as the
fixup delays the error message till after the assembler has quit due to
the other errors.
    
As the mov instruction shares the t2_so_imm_asmoperand mov instructions
with a non constant expression now match t2MOVi rather than t2MOVi16 so the
error message is slightly different.
    
Fixes PR28647

Differential Revision: https://reviews.llvm.org/D33492

llvm-svn: 304702
2017-06-05 09:37:12 +00:00
Sam Clegg c38e947e50 [WebAssembly] MC: Fix references to undefined externals in data section
Undefined externals don't need to have a size or an offset.
This was broken by r303915.  Added a test for this case.

This fixes the "Compile LLVM Torture (o)" step on the wasm
waterfall.

Differential Revision: https://reviews.llvm.org/D33803

llvm-svn: 304505
2017-06-02 01:05:24 +00:00