49316e40ba
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
...
Also add some test cases.
rdar://problem/9189829
llvm-svn: 128304
2011-03-25 22:19:07 +00:00
aaf2c69400
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
...
rdar://problem/9182892
llvm-svn: 128299
2011-03-25 19:35:37 +00:00
4fd2194638
A8.6.226 TBB, TBH:
...
Add two test cases.
llvm-svn: 128295
2011-03-25 18:40:21 +00:00
b35548f44d
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
...
t2LDREX/t2STREX instructions. Add two test cases.
llvm-svn: 128293
2011-03-25 18:29:49 +00:00
6f4c9425eb
MC: Improve some diagnostics on uses of '.' pseudo-symbol.
...
llvm-svn: 128289
2011-03-25 17:47:17 +00:00
aa84d41dfc
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
...
rdar://problem/9184053
llvm-svn: 128285
2011-03-25 17:31:16 +00:00
757ca69770
Also need to handle invalid imod values for CPS2p.
...
rdar://problem/9186136
llvm-svn: 128283
2011-03-25 17:03:12 +00:00
a52143bff3
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
...
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
llvm-svn: 128252
2011-03-25 01:09:48 +00:00
72f4a95144
delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.
...
llvm-svn: 128249
2011-03-25 00:17:42 +00:00
ceef55466a
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since
...
the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add
test cases for that.
llvm-svn: 128247
2011-03-24 23:42:31 +00:00
73193f2475
The ARM disassembler was confused with the 16-bit tSTMIA instruction.
...
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.
llvm-svn: 128246
2011-03-24 23:21:14 +00:00
9302df0ad9
Handle the added VBICiv*i* NEON instructions, too.
...
llvm-svn: 128243
2011-03-24 22:04:39 +00:00
6469ca0c33
T2 Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
llvm-svn: 128240
2011-03-24 21:36:56 +00:00
dd9eb21c3f
Plug a leak in the arm disassembler and put the tests back.
...
llvm-svn: 128238
2011-03-24 21:14:28 +00:00
f170f8bff6
Add asm parsing support w/ testcases for strex/ldrex family of instructions
...
llvm-svn: 128236
2011-03-24 21:04:58 +00:00
471f5aa233
Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'.
...
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.
llvm-svn: 128235
2011-03-24 20:56:23 +00:00
8bbc12824a
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
...
Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
2011-03-24 20:42:48 +00:00
c5207f7167
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
...
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
llvm-svn: 128226
2011-03-24 18:40:38 +00:00
1dd041083d
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
...
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
llvm-svn: 128220
2011-03-24 17:04:22 +00:00
0f5d52d658
Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
llvm-svn: 128191
2011-03-24 01:40:42 +00:00
1de8cc6f95
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
...
We now tag them as IndexModePost.
llvm-svn: 128189
2011-03-24 01:07:26 +00:00
f949d8e13d
The r128103 fix to cope with the removal of addressing modes from the MC instructions
...
were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
llvm-svn: 128186
2011-03-24 00:28:38 +00:00
122a6304ef
Add disassembly test cases for:
...
A8.6.292 VCMPE
llvm-svn: 128120
2011-03-22 23:08:56 +00:00
30350cdbdf
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
...
We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530 .
llvm-svn: 128113
2011-03-22 22:28:49 +00:00
0cf62f5045
Add one more test case for VFP Load/Store Multiple (vpop).
...
llvm-svn: 128106
2011-03-22 20:21:08 +00:00
230268261b
A8.6.399 VSTM:
...
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
llvm-svn: 128103
2011-03-22 20:00:10 +00:00
1557fd6d39
Write the section table and the section data in the same order that
...
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.
llvm-svn: 127972
2011-03-20 18:44:20 +00:00
0c5f670fe7
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
...
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
llvm-svn: 127935
2011-03-19 01:16:20 +00:00
1d2f5cebe4
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
...
llvm-svn: 127917
2011-03-18 22:50:18 +00:00
3fbfcc0e1e
Support explicit argument forms for the X86 string instructions.
...
For now, only the default segments are supported.
llvm-svn: 127875
2011-03-18 11:59:40 +00:00
e387f8a5e9
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
...
Remove the offending logic and update the test cases.
llvm-svn: 127843
2011-03-18 00:38:03 +00:00
221a014ea3
It used to be that t_addrmode_s4 was used for both:
...
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1
It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos). Modify the
disassembler to reflect the change, and add relevant tests.
llvm-svn: 127833
2011-03-17 22:04:05 +00:00
f1d62cfc8f
MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have
...
been removed.
llvm-svn: 127812
2011-03-17 16:25:24 +00:00
07de07eeea
Fix handling of @IDNTPOFF relocations, they need to get STT_TLS.
...
While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too.
llvm-svn: 127780
2011-03-17 00:35:10 +00:00
a4c3154fca
There were two issues fixed:
...
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
llvm-svn: 127707
2011-03-15 22:27:33 +00:00
f2f4837de3
Basic sanity checks to ensure that 2- and 3-byte
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VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
llvm-svn: 127647
2011-03-15 01:32:46 +00:00
7a2873dfbe
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
...
register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
llvm-svn: 127642
2011-03-15 01:13:17 +00:00
338d362200
Roll r127459 back in:
...
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127498
2011-03-11 21:52:04 +00:00
94ccb27b43
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
...
created from the", it broke some GCC test suite tests.
llvm-svn: 127477
2011-03-11 19:30:30 +00:00
cc27b3acc4
Optimize trivial branches in CodeGenPrepare, which often get created from the
...
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127459
2011-03-11 04:54:27 +00:00
9363d41f14
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
...
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
llvm-svn: 127354
2011-03-09 20:01:14 +00:00
5e57137e87
* Correct encoding for VSRI.
...
* Add tests for VSRI and VSLI.
llvm-svn: 127297
2011-03-09 00:33:17 +00:00
a7f303de71
Correct the encoding for VRSRA and VSRA instructions.
...
llvm-svn: 127294
2011-03-09 00:00:35 +00:00
e313f16ad9
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
...
* Update the NEON shift instruction test to expect what 'as' produces.
llvm-svn: 127293
2011-03-08 23:48:09 +00:00
a259686db1
A few more tests for instruction encodings.
...
llvm-svn: 127209
2011-03-08 02:51:48 +00:00
77ad1dc56d
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
...
expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
62f759791a
Be nice to Xcore and the XMOS assembler and avoid quoting section names
...
that contain only letters, digits and the characters "_" and ".".
llvm-svn: 127028
2011-03-04 20:03:14 +00:00
5aa4c68eca
Followup to r126970: add 64-bit encoding tests for str with reg operand.
...
llvm-svn: 126987
2011-03-04 04:06:47 +00:00
f63614a982
PR9377: Handle x86 str with register operand in a way consistent with gas.
...
llvm-svn: 126970
2011-03-04 00:10:17 +00:00
852ab890b5
Bug#9033: For the ELF assembler output, always quote the section name.
...
llvm-svn: 126963
2011-03-03 22:31:08 +00:00
d92d17bf67
PR9352: Always emit a relocation for weak symbols. Not emitting relocations
...
for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.
llvm-svn: 126933
2011-03-03 07:24:36 +00:00
6f6d739b6e
TableGen should not ignore BX instructions for the ARM disassembler. pr9368.
...
llvm-svn: 126931
2011-03-03 07:19:52 +00:00
ec84568904
pr9367: Add missing predicated BLX instructions.
...
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
llvm-svn: 126915
2011-03-03 01:41:01 +00:00
b8b6041734
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
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Patch by Ted Kremenek!
llvm-svn: 126895
2011-03-02 23:08:33 +00:00
3b1459b810
Narrow right shifts need to encode their immediates differently from a normal
...
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
58775fea6f
Fix the arm's disassembler for blx that was building an MCInst without the
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needed two predicate operands before the imm operand.
llvm-svn: 126662
2011-02-28 18:46:31 +00:00
78178749e9
split this test into arch specific pieces, so the ARM
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test isn't run when the arm backend isn't built. This
fixes PR9327
llvm-svn: 126500
2011-02-25 19:06:35 +00:00
afb36fad99
Restore r125595 (reverted in r126336) with modifications:
...
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.
llvm-svn: 126443
2011-02-24 21:59:22 +00:00
b52040da17
Move arch specific tests in arch specific directories.
...
llvm-svn: 126401
2011-02-24 19:06:27 +00:00
fe4858f269
Remove file. Previous commit deleted content, but left the file around.
...
llvm-svn: 126337
2011-02-23 21:43:31 +00:00
0c03a3a146
Revert r125595, which is an X86-only undocumented assembly syntax extension
...
enabled for all targets. Non-X86 targets should not have this behavior
enabled by default.
Joerg, if you would like to resubmit with the behavior conditionalized to be
X86-ELF only, that's fine.
llvm-svn: 126336
2011-02-23 21:26:51 +00:00
9e18e96264
Put in the symbol table symbols only used in a .globl statement.
...
Fixes PR9292.
llvm-svn: 126330
2011-02-23 20:22:07 +00:00
34770edf43
Fixed a bug in the enhanced disassembler that caused
...
it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
llvm-svn: 126302
2011-02-23 03:31:28 +00:00
b7e635dcad
Use the same (%dx) hack for in[bwl] as for out[bwl].
...
llvm-svn: 126244
2011-02-22 20:40:09 +00:00
c1b7775e0f
Added a testcase for the enhanced disassembly bug
...
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
llvm-svn: 126182
2011-02-22 02:19:18 +00:00
60e7629258
Recognize loopz and loopnz as aliases for loope and loopne.
...
From Dimitry Andric.
llvm-svn: 126168
2011-02-22 00:43:07 +00:00
e39062199e
Implement xgetbv and xsetbv.
...
Patch by Jai Menon.
llvm-svn: 126165
2011-02-22 00:35:18 +00:00
37d5484d18
Handle FK_PCRel_1 and add a test case for this and FK_PCRel_4.
...
llvm-svn: 126157
2011-02-21 23:25:41 +00:00
f849bf81bd
Add some limited support for labels in org directives. Hopefully enough to fix
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PR9245.
llvm-svn: 126091
2011-02-20 20:20:07 +00:00
47ffd35bea
implement PR9264: disambiguating 'bt mem, imm' as a btl.
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This is reasonable to do since all bt-mem forms do the
same thing.
llvm-svn: 126047
2011-02-19 21:06:36 +00:00
9cd43977c3
Add assembly parsing support for "msr" and also fix its encoding. Also add
...
testcases for the disassembler to make sure it still works for "msr".
llvm-svn: 125948
2011-02-18 19:45:59 +00:00
f69c80bac2
Recognize monitor/mwait with explicit register arguments
...
llvm-svn: 125805
2011-02-18 00:48:11 +00:00
889a508157
Recognize leavel and leaveq aliases for leave.
...
Validate encoding of leave in 64bit mode.
llvm-svn: 125795
2011-02-17 23:36:39 +00:00
490d02a334
Gas is very inconsistent about when a relaxation/relocation is needed. Do
...
the right thing and stop trying to copy it. Fixes PR8944.
llvm-svn: 125648
2011-02-16 03:25:55 +00:00
58ac6e1677
Add support for pushsection and popsection. Patch by Joerg Sonnenberger.
...
llvm-svn: 125629
2011-02-16 01:08:29 +00:00
4e0f4957bc
Add support for parsing [expr].
...
This is submitted by Joerg Sonnenberger and fixes his PR8685.
llvm-svn: 125595
2011-02-15 20:43:39 +00:00
90d1dfe4c6
Fix encoding and add parsing support for the arm/thumb CPS instruction:
...
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
2406b7d179
Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.
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These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.
llvm-svn: 125446
2011-02-12 23:24:13 +00:00
6e2e29bd11
Do AsmMatcher operand classification per-opcode.
...
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.
llvm-svn: 125245
2011-02-10 00:08:28 +00:00
4ebf471c9b
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
...
llvm-svn: 125127
2011-02-08 22:39:40 +00:00
7b7caf51e9
Support for .ifdef / .ifndef in the assembler parser. Patch by Joerg Sonnenberger.
...
llvm-svn: 125120
2011-02-08 22:29:56 +00:00
36dd43fda6
Add support for parsing dmb/dsb instructions
...
llvm-svn: 125055
2011-02-07 22:09:15 +00:00
202630c6ee
Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage
...
failures with relocations.
The code committed is a first cut at compatibility for emitted relocations in
ELF .o.
Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.
Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass
Added reminder fixme to tests for future conversion to .s form.
llvm-svn: 124996
2011-02-07 01:11:15 +00:00
4761fba833
Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to
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5 to match the current doc.
Added FIXME reminder Make it really configurable later.
llvm-svn: 124899
2011-02-04 21:41:11 +00:00
d2e2f56c36
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
...
(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
llvm-svn: 124895
2011-02-04 19:47:15 +00:00
2ea68db927
Fix test for non-darwin targets.
...
llvm-svn: 124640
2011-02-01 01:16:18 +00:00
775eec2280
PR9030: Fix disassembly of ARM "mov pc, lr" instruction.
...
Patch by Jyun-Yan You.
llvm-svn: 124492
2011-01-28 17:50:30 +00:00
7e9e290952
Add support for parsing .float
...
llvm-svn: 124485
2011-01-28 14:20:32 +00:00
4ada0d9164
PR8951: Support for .equiv in integrated assembler, patch by Jörg Sonnenberger!
...
llvm-svn: 124467
2011-01-28 03:04:41 +00:00
bb8420a070
Fix PLD encoding.
...
llvm-svn: 124458
2011-01-27 23:48:34 +00:00
ed5efb4053
Add support for specifying register name in cfi-register/offset/def
...
as well as register number.
llvm-svn: 124379
2011-01-27 17:16:37 +00:00
ce0af9c961
Add encoding testcases for ARM vcvtr variations
...
llvm-svn: 124289
2011-01-26 13:53:38 +00:00
178c1e0c9b
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
...
llvm-svn: 124288
2011-01-26 13:28:14 +00:00
78c9f78fc9
Jörg Sonnenberger noticed that we were missing this test.
...
llvm-svn: 124139
2011-01-24 19:40:38 +00:00
689939e648
Handle strings in section names the same way as gas:
...
* If the name is a single string, we remove the quotes
* If the name starts without a quote, we include any quotes in the name
llvm-svn: 124127
2011-01-24 18:02:54 +00:00
b3eca9bb71
Add support for the --noexecstack option.
...
llvm-svn: 124077
2011-01-23 17:55:27 +00:00
8bac423ddb
Add support for lowercase variants.
...
llvm-svn: 124071
2011-01-23 16:11:25 +00:00
4b7b7fba38
Delay the creation of eh_frame so that the user can change the defaults.
...
Add support for SHT_X86_64_UNWIND.
llvm-svn: 124059
2011-01-23 05:43:40 +00:00
4bd612384a
Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",
...
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.
llvm-svn: 123975
2011-01-21 14:07:40 +00:00
1f69de3983
Add testcases for clz encoding
...
llvm-svn: 123937
2011-01-20 19:27:16 +00:00
e965f06f7f
Fix the encoding and parsing of clrex instruction
...
llvm-svn: 123936
2011-01-20 19:18:32 +00:00
d8f9b37f31
Add cdp/cdp2 instructions for thumb/thumb2
...
llvm-svn: 123929
2011-01-20 18:32:09 +00:00
33461ecc82
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
...
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.
llvm-svn: 123927
2011-01-20 18:06:58 +00:00
4d4b490fb7
Add mcr*2 and mr*c2 support to thumb2 targets
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llvm-svn: 123919
2011-01-20 16:58:48 +00:00
cf99dc7eb9
Add mcr* and mr*c support to thumb targets
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llvm-svn: 123917
2011-01-20 16:35:57 +00:00
d6335ce508
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
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llvm-svn: 123837
2011-01-19 16:56:52 +00:00
dac7a0174e
When matching asm operands, always try to match the most restricted type first.
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Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous. This
is tricky to resolve since neither is a subset of the other.
XFAIL the test for now. The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.
llvm-svn: 123786
2011-01-18 23:01:21 +00:00
2082057b18
Create two new generic classes to represent the following VMRS/VMSR variations:
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vmrs reg, fpexc
vmrs reg, fpsid
vmsr fpexc, reg
vmsr fpsid, reg
llvm-svn: 123783
2011-01-18 21:58:20 +00:00
cba727f291
Fix MRS encoding for arm and thumb.
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llvm-svn: 123778
2011-01-18 21:31:35 +00:00
e86a7ad01a
Fix the encoding of t2ISB by using the right class and also parse it correctly
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llvm-svn: 123776
2011-01-18 21:17:09 +00:00
e6290ccf9b
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
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llvm-svn: 123772
2011-01-18 20:55:11 +00:00
7f639c11d7
Add support for parsing and encoding ARM's official syntax for the BFI instruction
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llvm-svn: 123770
2011-01-18 20:45:56 +00:00
66e91d4a58
McARM: Start marking T2 address operands as such, for the benefit of the parser.
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llvm-svn: 123722
2011-01-18 03:06:03 +00:00
ec517cdf24
Update tests.
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llvm-svn: 123591
2011-01-16 18:02:57 +00:00
d4a5c05c97
Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
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- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
llvm-svn: 123424
2011-01-14 02:38:49 +00:00
ec47597ecd
As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends.
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llvm-svn: 123407
2011-01-13 22:38:16 +00:00
965b3c7323
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
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in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
llvm-svn: 123369
2011-01-13 07:58:56 +00:00
e6ff05c59d
Sort the register list based on the *actual* register numbers rather than the
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enum values we give to them. <rdar://problem/8823730>
llvm-svn: 123321
2011-01-12 21:20:59 +00:00
9c5b65d289
1. Support ELF pcrel relocations for movw/movt:
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R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
llvm-svn: 123294
2011-01-12 00:19:25 +00:00
1f7bc0707d
Workaround for bug 8721.
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.s Test added.
llvm-svn: 123292
2011-01-11 23:53:41 +00:00
abd2dfd3dc
Fix PR8946, a missing reg/reg form of movdqu.
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llvm-svn: 123242
2011-01-11 17:04:55 +00:00
9d944b3fcc
McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the
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carry setting flag from the mnemonic.
Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.
llvm-svn: 123238
2011-01-11 15:59:50 +00:00
c0e8756ba9
McARM: Flush out hard coded known non-predicated mnemonic list.
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llvm-svn: 123189
2011-01-10 21:01:03 +00:00
9f9a10691a
Correctly disassemble truncated asm.
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Patch by Richard Simth.
llvm-svn: 122962
2011-01-06 16:48:42 +00:00
f02ca16ba7
Convert MC tests to .s so codegen changes won't break them.
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llvm-svn: 122786
2011-01-03 23:47:14 +00:00
3686473578
Fix PR8878.
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llvm-svn: 122658
2011-01-01 19:05:35 +00:00
ee0432ce08
Add another non-commutable instruction that gas accepts commuted forms for.
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Fixes PR8861.
llvm-svn: 122641
2010-12-30 22:10:49 +00:00
ab14a6f174
MC/Mach-O/Thumb: Set the thumb bit in the symbol table.
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llvm-svn: 122630
2010-12-29 14:14:06 +00:00
46a5b05207
Correctly encode pcrel|indirect.
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llvm-svn: 122624
2010-12-29 04:31:26 +00:00
563301dfdb
Fix bug when trying to output uint16_t or uint32_t.
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llvm-svn: 122615
2010-12-29 02:30:49 +00:00
290d71671e
Implement cfi_def_cfa. Also don't convert to dwarf reg numbers twice. Looks
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like 6 is a fixed point of that and so the previous tests were OK :-)
llvm-svn: 122614
2010-12-29 01:42:56 +00:00
426e68f793
Implement cfi_def_cfa_register.
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llvm-svn: 122612
2010-12-29 00:26:06 +00:00
86d347dd31
Initial .cfi_offset implementation.
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llvm-svn: 122611
2010-12-29 00:09:59 +00:00
6bbfb6c06c
Don't produce a "DW_CFA_advance_loc 0".
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llvm-svn: 122609
2010-12-28 23:38:03 +00:00
85d91982ca
Implement .cfi_remember_state and .cfi_restore_state.
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llvm-svn: 122602
2010-12-28 18:36:23 +00:00
736a35d9ab
Relax address updates in the eh_frame section.
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llvm-svn: 122591
2010-12-28 05:39:27 +00:00
a75b87b55a
Start adding basic support for emitting the call frame instructions.
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llvm-svn: 122590
2010-12-28 04:15:37 +00:00
1de2dd0e5e
Add support for .cfi_lsda.
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llvm-svn: 122584
2010-12-27 15:56:22 +00:00
a895c69431
MC/Mach-O/Thumb: Select appropriate relocation types for Thumb.
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llvm-svn: 122583
2010-12-27 14:49:49 +00:00
8fc59a682f
Handle reloc_riprel_4byte_movq_load. Should make the bots happy.
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llvm-svn: 122579
2010-12-27 02:03:24 +00:00
2ac8355ecd
Add support for the same encodings of the personality function that gnu as
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supports.
llvm-svn: 122577
2010-12-27 00:36:05 +00:00
9ae2d05d45
Add support for @note. Patch by Jörg Sonnenberger.
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llvm-svn: 122568
2010-12-26 21:30:59 +00:00
9141b611ad
Add basic support for .cfi_personality.
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llvm-svn: 122566
2010-12-26 20:20:31 +00:00
03a102bff3
Generalize a previous change, fixing PR8855 - an valid large immediate
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rejected by the mc assembler.
llvm-svn: 122557
2010-12-25 21:36:35 +00:00
7f2bb4dcae
MC/Mach-O/ARM: Start handling some Thumb branches.
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llvm-svn: 122547
2010-12-24 16:41:46 +00:00
fa3c6f148c
In llvm-mc parse a Hash token as a full line comment. Allows handling of
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preprocessed .s files and matches darwin gas. rdar://8798690
Also fix a comment on the next line of AsmParser.cpp after this new code.
llvm-svn: 122531
2010-12-24 00:12:02 +00:00
ac8173cf71
MC/Mach-O/ARM: Don't try to use scattered relocs for BR24 fixups.
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llvm-svn: 122441
2010-12-22 21:26:43 +00:00
1af01a69d4
Add reduced test from 8845.
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llvm-svn: 122438
2010-12-22 21:15:13 +00:00
45140d2efc
MC/Mach-O/ARM: We always use the SECTDIFF reloc type on ARM, which is
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esp. important given that the LOCAL_SECTDIFF enumeration got redefined.
llvm-svn: 122412
2010-12-22 16:52:19 +00:00
9ccf843a61
MC/Mach-O/ARM: Add enough relocation logic to get BR24 relocations.
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llvm-svn: 122407
2010-12-22 16:19:24 +00:00
Johnny Chen