Commit Graph

227212 Commits

Author SHA1 Message Date
Davide Italiano 08f8f21b91 [IR/Verifier] Fix (yet another) crash.
We need to check that if we reference a retainedType from
DICompileUnit we're actually referencing a DICompositeType.

llvm-svn: 265752
2016-04-08 00:01:32 +00:00
Justin Lebar 25c36fd61b [CUDA] Tweak math forward declares so we're compatible with libstdc++4.9.
Summary:
See comments in patch; we were assuming that some stdlib math functions
would be defined in namespace std, when in fact the spec says they
should be defined in the global namespace.  libstdc++4.9 became more
conforming and broke us.

This new implementation seems to cover the known knowns.

Reviewers: rsmith

Subscribers: cfe-commits, tra

Differential Revision: http://reviews.llvm.org/D18882

llvm-svn: 265751
2016-04-07 23:55:53 +00:00
Rui Ueyama 6c8b0c1b96 Use EM_NONE instead of 0 to represent an invalid value. NFC.
llvm-svn: 265750
2016-04-07 23:54:33 +00:00
Quentin Colombet e16f561d91 [RegBankSelect] Add a few debug statements.
llvm-svn: 265749
2016-04-07 23:53:55 +00:00
Rui Ueyama d86ec30168 ELF: Add --build-id=sha1 option.
llvm-svn: 265748
2016-04-07 23:51:56 +00:00
Quentin Colombet 9a2ae85e67 [RegisterBankInfo] Add print and dump method to the InstructionMapping
helper class.

llvm-svn: 265747
2016-04-07 23:31:58 +00:00
Quentin Colombet e087c9fc12 [RegisterBankInfo] Add print and dump method to the ValueMapping helper
class.

llvm-svn: 265746
2016-04-07 23:25:43 +00:00
Quentin Colombet 03c419628e [MachineInstr] Teach the print method about RegisterBank.
Properly print either the register class or the register bank or a
virtual register.
Get rid of a few ifdefs in the process.

llvm-svn: 265745
2016-04-07 23:18:11 +00:00
Peter Collingbourne e217660591 ELF: Ignore --detect-odr-violations flag.
Differential Revision: http://reviews.llvm.org/D18877

llvm-svn: 265744
2016-04-07 23:15:50 +00:00
Quentin Colombet 88f7f6bc4f [AArch64] Fix a typo in the register class to register bank mapping.
For GPR family we want the GPR register bank, not FPR!

llvm-svn: 265743
2016-04-07 23:10:14 +00:00
Quentin Colombet f4e36faa9c [RegisterBankInfo] Escap \@ in r265741. [-Wdocumentation]
llvm-svn: 265742
2016-04-07 23:08:52 +00:00
Quentin Colombet c68b020412 [RegisterBankInfo] Change the semantic of recordRegBankForType.
Now, recordRegBankForType records only the first register bank that
covers a type instead of the last. This behavior can, nevertheless, be
override with the additional Force parameter to force the update.

llvm-svn: 265741
2016-04-07 23:02:00 +00:00
David Blaikie 97a42caeb0 llvm-dwarfdump: Use deque rather than vector to preserve object reference/pointer identity
TUs in each unit refer to the unit they are in, if the unit is moved
this reference is invalidated & things break.

No test case because UB isn't testable - ASan would likely catch this on
a large enough test case (just needs to have enough TUs that a
reallocation of the vector would occur) but didn't seem worthwhile. Up
for debate/revisiting if anyone feels strongly.

llvm-svn: 265740
2016-04-07 22:59:58 +00:00
Quentin Colombet ac40034e06 [RegisterBankInfo] Strengthen getInstrMappingImpl.
Teach the target independent code how to take advantage of type
information to get the mapping of an instruction.

llvm-svn: 265739
2016-04-07 22:52:49 +00:00
Adrian McCarthy f9f3609704 Fix TestImport for Windows by ensuring backslashes in the directory paths are properly escaped in Python.
The Python import works by ensuring the directory of the module or package is in sys.path, and then it does a Python `import foo`.  The original code was not escaping the backslashes in the directory path, so this wasn't working.

Differential Revision: http://reviews.llvm.org/D18873

llvm-svn: 265738
2016-04-07 22:52:12 +00:00
Rui Ueyama 3a41be277a ELF: Implement --build-id=md5.
Previously, we supported only one hash function, FNV-1, so
BuildIdSection directly handled hash computation. In this patch,
I made BuildIdSection an abstract class and defined two subclasses,
BuildIdFnv1 and BuildIdMd5.

llvm-svn: 265737
2016-04-07 22:49:21 +00:00
Quentin Colombet e918006a87 [RegisterBankInfo] Add a way to record what register bank covers a
specific type.

This will be used to find the default mapping of the instruction.
Also, this information is recorded, instead of computed, because it is
expensive from a type to know which register bank maps it.
Indeed, we need to iterate through all the register classes of all the
register banks to find the one that maps the given type.

llvm-svn: 265736
2016-04-07 22:45:42 +00:00
Quentin Colombet c8d612f6fd [RegisterBankInfo] Introduce getRegBankFromConstraints as an helper
method.

NFC.

The refactoring intends to make the code more readable and expose
more features to potential derived classes.

llvm-svn: 265735
2016-04-07 22:35:03 +00:00
Quentin Colombet 2445dc1916 [TargetRegisterInfo] Refactor the code to use BitMaskClassIterator.
llvm-svn: 265734
2016-04-07 22:16:56 +00:00
Quentin Colombet cf477ffc58 [RegisterBankInfo] Refactor the code to use BitMaskClassIterator.
llvm-svn: 265733
2016-04-07 22:08:56 +00:00
Jason Molenda 7d0027627b In GDBRemoteCommunicationClient::GetHostInfo, don't set the
os to "ios" or "macosx" if it is unspecified.  For environments
where there genuinely is no os, we don't want to errantly 
convert that to ios/macosx, e.g. bare board debugging.

Change PlatformRemoteiOS, PlatformRemoteAppleWatch, and
PlatformRemoteAppleTV to not create themselves if we have
an unspecified OS.  Same problem - these are not appropriate
platforms for bare board debugging environments.

Have Process::Attach's logging take place if either 
process or target logging is enabled.

<rdar://problem/25592378> 

llvm-svn: 265732
2016-04-07 22:00:55 +00:00
Mehdi Amini a797877a7e Const correctness for BranchProbabilityInfo (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265731
2016-04-07 21:59:28 +00:00
Quentin Colombet 0a680bd703 [TargetRegisterInfo] Introduce a helper class, BitMaskClassIterator, to
iterate over register class bitmask.

Thanks to this helper class, it would not require for each user of the
register classes bitmask to actually know how they are represents.
Moreover, it will make the code much easier to read.

llvm-svn: 265730
2016-04-07 21:55:21 +00:00
Mehdi Amini 4a9a1816cb Rename parameter I to Index for WriteCombinedGlobalValueSummary() (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265729
2016-04-07 21:49:31 +00:00
Richard Smith 351241c83e Replace Sema-level implementation of -fassume-sane-operator-new with a
CodeGen-level implementation. Instead of adding an attribute to clang's
FunctionDecl, add the IR attribute directly. This means a module built with
this flag is now compatible with code built without it and vice versa.

This change also results in the 'noalias' attribute no longer being added to
calls to operator new in the IR; it's now only added to the declaration. It
also fixes a bug where we failed to add the attribute to the 'nothrow' versions
(because we didn't implicitly declare them, there was no good time to inject a
fake attribute).

llvm-svn: 265728
2016-04-07 21:46:12 +00:00
Quentin Colombet aac71a4a0e [RegBankSelect] Reuse RegisterBankInfo logic to get to the register bank
from a register.
On top of duplicating the logic, it was buggy! It would assert on
physical registers, since MachineRegisterInfo does not have any
information regarding register classes/banks for them.

llvm-svn: 265727
2016-04-07 21:32:23 +00:00
Amaury Sechet c53ad4f3b2 Do not select EhPad BB in MachineBlockPlacement when there is regular BB to schedule
Summary:
EHPad BB are not entered the classic way and therefor do not need to be placed after their predecessors. This patch make sure EHPad BB are not chosen amongst successors to form chains, and are selected as last resort when selecting the best candidate.

EHPad are scheduled in reverse probability order in order to have them flow into each others naturally.

Reviewers: chandlerc, majnemer, rafael, MatzeB, escha, silvas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17625

llvm-svn: 265726
2016-04-07 21:29:39 +00:00
Quentin Colombet 846219ae10 [AArch64] Get rid of some GlobalISel ifdefs.
llvm-svn: 265725
2016-04-07 21:24:40 +00:00
Rui Ueyama 5d92af65d3 Sort options.
llvm-svn: 265724
2016-04-07 21:10:42 +00:00
Rui Ueyama c4354a3c18 ELF: Define -S as an alias for --strip-debug.
llvm-svn: 265723
2016-04-07 21:10:09 +00:00
Rui Ueyama fc6a4b045f ELF: Add --strip-debug option.
If --strip-debug option is given, then all sections whose names start
with ".debug" are removed from output.

llvm-svn: 265722
2016-04-07 21:04:51 +00:00
Quentin Colombet 07334f05de [TargetRegisterInfo] Fix the comment of SuperRegClassIterator::getMask.
llvm-svn: 265721
2016-04-07 21:04:30 +00:00
Quentin Colombet 6cc73ce808 [AArch64] gcc does not like litteral without quotes even on preprocessor macros.
llvm-svn: 265720
2016-04-07 20:49:15 +00:00
Quentin Colombet 789ad56248 [AArch64][CallLowering] Do not build the API if GlobalISel is not built.
This gets rid of some ifdefs and dummy implementations that were here
just to fill the blanks.

llvm-svn: 265719
2016-04-07 20:47:51 +00:00
Richard Smith a1ddf5e744 [modules] Allow differences in flags that only affect preprocessor predefines
(and __has_feature checks) between explicitly-specified module files and the
current compilation.

llvm-svn: 265718
2016-04-07 20:47:37 +00:00
Rui Ueyama 8c76487ee5 ELF: Add --no-gnu-unique option.
When the option is specified, then all STB_GNU_UNIQUE symbols are
converted to STB_GLOBAL symbols.

llvm-svn: 265717
2016-04-07 20:41:41 +00:00
Quentin Colombet d4131814b3 [GlobalISel] Add RegBankSelect hooks into the pass pipeline.
Now, RegBankSelect will happen after the IRTranslation and the target
may optionally add additional passes in between.

llvm-svn: 265716
2016-04-07 20:27:33 +00:00
Evgeniy Stepanov eb37fcbc87 [sanitizer] Fix sem_init_glibc.cc test on __HAVE_64B_ATOMIC arches.
glibc can use one of 2 layouts for semaphores: architectures that
don't HAVE_64B_ATOMIC use an uint32_t field with semaphore value,
then a private field, then a waiting thread count field - this is
the layout currently assumed by the test. However, HAVE_64B_ATOMIC
arches use a fused uint64_t field that contains the value in low bits
and waiting thread count in high bits, followed by a private field.

This resulted in taking private field from the wrong offset on 64-bit
atomic platforms (the test still passed, but didn't actually test
the private field). On big-endian platforms, this resulted in a fail,
since the first 4 bytes overlay the thread count field, and not
the value field.

Found while porting ASan to s390x.

Patch by Marcin Kościelnicki.

llvm-svn: 265715
2016-04-07 20:26:28 +00:00
Mike Aizatsky 87b30a0ef2 [sancov] updaing android test after enabling cc edge pruning
llvm-svn: 265714
2016-04-07 20:21:21 +00:00
Konstantin Zhuravlyov f8a81f869f [AMDGPU] Implement get_local_size for amdgcn--amdhsa triple
Differential Revision: http://reviews.llvm.org/D18284

llvm-svn: 265713
2016-04-07 19:54:19 +00:00
Manman Ren 7ed4f988c1 [ObjC kindof] Use type bound to filter out the candidate methods.
rdar://21306753

llvm-svn: 265712
2016-04-07 19:32:24 +00:00
Manman Ren d2a3cd7261 NFC: simplify code in BuildInstanceMessage.
Instead of searching the global pool multiple times: in
LookupFactoryMethodInGlobalPool, LookupInstanceMethodInGlobalPool,
CollectMultipleMethodsInGlobalPool, and AreMultipleMethodsInGlobalPool,
we now collect the method candidates in CollectMultipleMethodsInGlobalPool
only, and other functions will use the collected method set.

This commit adds parameter "Methods" to AreMultipleMethodsInGlobalPool,
and SelectBestMethod. It also changes the implementation of
CollectMultipleMethodsInGlobalPool to collect the desired kind first, if none is
found, to collect the other kind. This avoids the need to call both
LookupFactoryMethodInGlobalPool and LookupInstanceMethodInGlobalPool.

llvm-svn: 265711
2016-04-07 19:30:20 +00:00
Rui Ueyama f8baa66056 ELF: Implement --start-lib and --end-lib
start-lib and end-lib are options to link object files in the same
semantics as archive files. If an object is in start-lib and end-lib,
the object is linked only when the file is needed to resolve
undefined symbols. That means, if an object is in start-lib and end-lib,
it behaves as if it were in an archive file.

In this patch, I introduced a new notion, LazyObjectFile. That is
analogous to Archive file type, but that works for a single object
file instead of for an archive file.

http://reviews.llvm.org/D18814

llvm-svn: 265710
2016-04-07 19:24:51 +00:00
Jan Vesely 43b7b5b846 AMDGPU/SI: Implement atomic load/store for i32 and i64
Standard load/store instructions with GLC bit set.

Reviewers: tstellardAMD, arsenm

Differential Revision: http://reviews.llvm.org/D18760

llvm-svn: 265709
2016-04-07 19:23:11 +00:00
Tom Stellard 9112758077 AMDGPU/SI: Add latency for export instructions
Reviewers: arsenm, nhaehnle

Subscribers: nhaehnle, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18599

llvm-svn: 265708
2016-04-07 18:30:05 +00:00
Quentin Colombet 40ad573d2c [RegBankSelect] Initial implementation for non-optimized output.
The pass walk through the machine function and assign the register banks
using the default mapping. In other words, there is no attempt to reduce
cross register copies.

llvm-svn: 265707
2016-04-07 18:19:27 +00:00
Marshall Clow 89685ed0da Recommit r263036 with additional inlining, so that it will continue to work with existing system dylibs. Implements LWG#2583
llvm-svn: 265706
2016-04-07 18:13:41 +00:00
Derek Bruening a7685389c8 [sanitizer] Add early call handling to strlen interceptor
Summary:
The strlen interceptor is sometimes invoked too early for REAL(strlen) to
be initialized.  A special check is added to use internal_strlen for this
situation.

Reviewers: dim

Subscribers: llvm-commits, samsonov

Differential Revision: http://reviews.llvm.org/D18851

Change-Id: I3acc58f4abbae1904f25324abd84efea67aad0a2
llvm-svn: 265705
2016-04-07 18:07:09 +00:00
Quentin Colombet 42795bdc76 [RegisterBankInfo] Add more details on the expectation of
getInstrMapping.

llvm-svn: 265704
2016-04-07 18:07:07 +00:00
Quentin Colombet fe1ee4f9be [RegisterBankInfo] Provide a target independent helper function to guess
the mapping of an instruction on register bank.

For most instructions, it is possible to guess the mapping of the
instruciton by using the encoding constraints.
It remains instructions without encoding constraints.
For copy-like instructions, we try to propagate the information we get
from the other operands. Otherwise, the target has to give this
information.

llvm-svn: 265703
2016-04-07 18:01:19 +00:00