dffc542123
[mips] Set instruction itineraries of loads, stores and conditional moves.
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llvm-svn: 190219
2013-09-06 23:28:24 +00:00
e0fbb44a48
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
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llvm-svn: 190148
2013-09-06 12:41:17 +00:00
ff7beb1754
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
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llvm-svn: 188690
2013-08-19 19:08:03 +00:00
00fcf2e169
[mips] Rename accumulator register classes and FP register operands.
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llvm-svn: 188020
2013-08-08 21:54:26 +00:00
13e6ccf341
[mips] Rename register classes CPURegs and CPU64Regs.
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llvm-svn: 187832
2013-08-06 23:08:38 +00:00
c7e3998e45
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of
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instructions defined in MipsInstrInfo.td as codegen-only instructions.
llvm-svn: 187828
2013-08-06 23:01:10 +00:00
f8fff213d5
[mips] Define instruction itineraries IIArith and IILogic.
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No functionality change.
llvm-svn: 187468
2013-07-31 00:55:34 +00:00
643b398786
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
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llvm-svn: 187410
2013-07-30 10:12:14 +00:00
8bce21c154
[mips] Fix FP conditional move instructions to have explicit FP condition code
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register operands.
llvm-svn: 187242
2013-07-26 20:51:20 +00:00
55f69b302c
[mips] Fix floating point branch, comparison, and conditional move instructions
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to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.
No intended functionality change.
llvm-svn: 187233
2013-07-26 19:01:56 +00:00
64828a1f73
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
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llvm-svn: 186397
2013-07-16 10:07:14 +00:00
ece459bb66
[mips] Fix inefficient code generation.
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This patch eliminates the need to emit a constant move instruction when this
pattern is matched:
(select (setgt a, Constant), T, F)
The pattern above effectively turns into this:
(conditional-move (setlt a, Constant + 1), F, T)
llvm-svn: 176384
2013-03-01 21:52:08 +00:00
a4c0341514
Fix indentation.
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llvm-svn: 176380
2013-03-01 21:22:21 +00:00
a7a9fa1c16
[mips] Refactor conditional move instructions.
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llvm-svn: 171511
2013-01-04 19:16:38 +00:00
b2cc8a756f
[mips] Delete all floating point instruction classes that are no longer used.
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No functionality change.
llvm-svn: 170084
2012-12-13 02:05:02 +00:00
6262bbf819
[mips] Modify definitions of floating point conditional move instructions.
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No functionality change.
llvm-svn: 170080
2012-12-13 01:41:15 +00:00
97e179f9e4
[mips] Shorten predicate name.
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llvm-svn: 169579
2012-12-07 03:06:09 +00:00
02a346d11f
[mips] Remove unnecessary predicates.
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llvm-svn: 169577
2012-12-07 03:01:24 +00:00
d8ab16b86f
1. introduce MipsPat in place of Pat in order to exclude those from
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being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered
Patch by Reed Kotler.
llvm-svn: 158470
2012-06-14 21:03:23 +00:00
cdf4fd8267
This patch adds a predicate to existing mips32 and mips64 so that those
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instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
llvm-svn: 157234
2012-05-22 03:10:09 +00:00
ca41d13bbd
Add another peephole pattern for conditional moves.
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llvm-svn: 156460
2012-05-09 02:29:29 +00:00
71928e681b
Add disassembler to MIPS.
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Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
55059262aa
Revert r153924. There were buildbot failures.
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llvm-svn: 153925
2012-04-03 02:51:09 +00:00
e2498d014b
MIPS disassembler support.
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Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
f54f60f3ce
remove blanks, and some code format
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llvm-svn: 151625
2012-02-28 07:46:26 +00:00
dd6c1cd4e8
add Emacs tag and fix some comment error in file headers
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llvm-svn: 150775
2012-02-17 01:23:50 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
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-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
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expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
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llvm-svn: 142220
2011-10-17 18:43:19 +00:00
Akira Hatanaka