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147 Commits

Author SHA1 Message Date
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.

llvm-svn: 170661
 2012-12-20 04:20:09 +00:00
Akira Hatanaka c0ea0bb99b [mips] Refactor conditional branch instructions with one register operand. 
Separate encoding information from the rest.

llvm-svn: 170659
 2012-12-20 04:13:23 +00:00
Akira Hatanaka f71ffd29d9 [mips] Refactor conditional branch instructions with two register operands. 
Separate encoding information from the rest.

llvm-svn: 170657
 2012-12-20 04:10:13 +00:00
Akira Hatanaka 7d75f9e3d3 [mips] Change the order of template parameters. Move the default parameters to 
the end. 

llvm-svn: 170651
 2012-12-20 03:52:08 +00:00
Akira Hatanaka 244f9e874c [mips] Refactor shift instructions with register operands. Separate encoding 
information from the rest.

llvm-svn: 170650
 2012-12-20 03:48:24 +00:00
Akira Hatanaka 7f96ad325f [mips] Refactor shift immediate instructions. Separate encoding information 
from the rest.

llvm-svn: 170649
 2012-12-20 03:44:41 +00:00
Akira Hatanaka ab1b715bf2 [mips] Refactor arithmetic and logic instructions with immediate operands. 
Separate encoding information from the rest.

llvm-svn: 170648
 2012-12-20 03:40:03 +00:00
Akira Hatanaka 1b37c4af01 [mips] Refactor arithmetic and logic instructions. Separate encoding 
information from the rest.

llvm-svn: 170647
 2012-12-20 03:34:05 +00:00
Akira Hatanaka 73495897b1 [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and 
ArithLogicI as the instruction base classes.

llvm-svn: 170642
 2012-12-20 03:00:16 +00:00
Akira Hatanaka efdce0fb09 [mips] Delete nodes and instructions for dynamic alloca that are no longer in 
use.

llvm-svn: 169580
 2012-12-07 03:10:18 +00:00
Akira Hatanaka 97e179f9e4 [mips] Shorten predicate name. 
llvm-svn: 169579
 2012-12-07 03:06:09 +00:00
Akira Hatanaka 02a346d11f [mips] Remove unnecessary predicates. 
llvm-svn: 169577
 2012-12-07 03:01:24 +00:00
Akira Hatanaka bb6e74a2f1 [mips] Generate big GOT code. 
llvm-svn: 168460
 2012-11-21 20:40:38 +00:00
Akira Hatanaka 4f5ef21869 [mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables 
re-materialization of immediate loads.

llvm-svn: 167153
 2012-10-31 18:37:55 +00:00
Akira Hatanaka d03d68a3ba [mips] Add tail call instructions. 
llvm-svn: 166338
 2012-10-19 21:14:34 +00:00
David Chisnall 6a00ab4b5e Expose move to/from coprocessor instructions in MIPS64 mode. 
Note: [D]M{T,F}CP2 is just a recommended encoding.  Vendors often provide a
custom CP2 that interprets instructions differently and may wish to add their
own instructions that use this opcode.  We should ensure that this is easy to
do.  I will probably add a 'has custom CP{0-3}' subtarget flag to make this
easy: We want to avoid the GCC situation where every MIPS vendor makes a custom
fork that breaks every other MIPS CPU and so can't be merged upstream.

llvm-svn: 165711
 2012-10-11 10:21:34 +00:00
David Chisnall 3705125cc8 Improvements to MIPS64 assembler: 
- Teach it about dadd[i] instructions and move pseudo-instruction
- Make it parse the register names correctly (for N32 / N64)

llvm-svn: 165506
 2012-10-09 16:27:43 +00:00
Akira Hatanaka 3e7ba76157 Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and 
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.

No changes in functionality.

llvm-svn: 163960
 2012-09-15 01:52:08 +00:00
Jack Carter b3f3b17e16 The instruction DINS may be transformed into DINSU or DEXTM depending 
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword

llvm-svn: 163010
 2012-08-31 18:06:48 +00:00
Jack Carter cd6b0e1368 The instruction DEXT may be transformed into DEXTU or DEXTM depending 
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword

llvm-svn: 162782
 2012-08-28 20:07:41 +00:00
Jack Carter 120a30a732 Another 32 to 64 bit sign extension bug. 
The fields in the td definition were switched.

llvm-svn: 161607
 2012-08-09 19:43:18 +00:00
Jack Carter f4946cfbb9 The define for 64 bit sign extension neglected to 
initialize fields of the class that it used.

The result was nonsense code.

Before:
0000000000000000 <foo>:
   0:    00441100     0x441100
   4:    03e00008     jr    ra
   8:    00000000     nop

After:
0000000000000000 <foo>:
   0:    00041000     sll    v0,a0,0x0
   4:    03e00008     jr    ra
   8:    00000000     nop 

llvm-svn: 161377
 2012-08-07 00:35:22 +00:00
Jack Carter 612c66314c The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 
were using a class defined for 32 bit instructions and 
thus the instruction was for addiu instead of daddiu.

This was corrected by adding the instruction opcode as a 
field in the  base class to be filled in by the defs.

llvm-svn: 161359
 2012-08-06 23:29:06 +00:00
Jack Carter f649043aa5 Doubleword Shift Left Logical Plus 32 
Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63

Here is a description of DSLL:

Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits

Description: GPR[rd] <- GPR[rt] << (sa+32)

The 64-bit doubleword contents of GPR rt are shifted left, inserting
 zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.

This patch implements the direct object output of these instructions.

llvm-svn: 160277
 2012-07-16 15:14:51 +00:00
Akira Hatanaka efff7b763b Make register Mips::RA allocatable if not in mips16 mode. 
llvm-svn: 159971
 2012-07-10 00:19:06 +00:00
Akira Hatanaka d8ab16b86f 1. introduce MipsPat in place of Pat in order to exclude those from 
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470
 2012-06-14 21:03:23 +00:00
Akira Hatanaka f11571d90d Add definitions of 32/64-bit unaligned load/store instructions for Mips. 
llvm-svn: 157865
 2012-06-02 00:04:19 +00:00
Akira Hatanaka cdf4fd8267 This patch adds a predicate to existing mips32 and mips64 so that those 
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
 2012-05-22 03:10:09 +00:00
Akira Hatanaka 4167bb9346 Delete blank line. 
llvm-svn: 155030
 2012-04-18 18:47:17 +00:00
Akira Hatanaka 71928e681b Add disassembler to MIPS. 
Patch by Vladimir Medic. 

llvm-svn: 154935
 2012-04-17 18:03:21 +00:00
Akira Hatanaka 55059262aa Revert r153924. There were buildbot failures. 
llvm-svn: 153925
 2012-04-03 02:51:09 +00:00
Akira Hatanaka e2498d014b MIPS disassembler support. 
Patch by Vladimir Medic.

llvm-svn: 153924
 2012-04-03 02:20:58 +00:00
Akira Hatanaka 5350c24509 Changes for migrating to using register mask operands. 
llvm-svn: 151847
 2012-03-01 22:27:29 +00:00
Jia Liu f54f60f3ce remove blanks, and some code format 
llvm-svn: 151625
 2012-02-28 07:46:26 +00:00
Akira Hatanaka b049aef2d1 Add an option to use a virtual register as the global base register instead of 
reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register. 

example:

.cpload $25       // set $gp.
...
.cprestore 16     // store $gp to stack slot 16($sp).
...
jalr $25          // function call. clobbers $gp.
lw $gp, 16($sp)   // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25          // function call.
lw $gp, 16($sp)   // not emitted if $gp is not live after this instruction.
...

llvm-svn: 151402
 2012-02-24 22:34:47 +00:00
Akira Hatanaka 86d5fadd57 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. 
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908
 2012-01-25 03:01:35 +00:00
Akira Hatanaka 9f7ec1538f 64-bit sign extension in register instructions. 
llvm-svn: 148862
 2012-01-24 21:41:09 +00:00
Akira Hatanaka 3b775b8cc3 Rename immLUiOpnd. 
llvm-svn: 147519
 2012-01-04 03:09:26 +00:00
Akira Hatanaka b89a4bfe41 - Define base classes for Jump-and-link instructions and make 32-bit and 64-bit 
versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518
 2012-01-04 03:02:47 +00:00
Akira Hatanaka 695d113adc If target ABI is N64, LEA should be daddiu. 
llvm-svn: 147232
 2011-12-24 02:59:27 +00:00
Akira Hatanaka 4706ac9715 Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
 2011-12-20 23:56:43 +00:00
Akira Hatanaka 494fdf1499 32-to-64-bit sext_inreg pattern. 
llvm-svn: 147004
 2011-12-20 22:40:40 +00:00
Akira Hatanaka 8756816e6f Add 64-bit extload patterns. 
llvm-svn: 147003
 2011-12-20 22:36:08 +00:00
Akira Hatanaka 4e210691c0 32-to-64-bit sign extension pattern. 
llvm-svn: 146995
 2011-12-20 22:06:20 +00:00
Akira Hatanaka db47e0c49d Add patterns for matching immediates whose lower 16-bit is cleared. These 
patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900
 2011-12-19 20:21:18 +00:00
Akira Hatanaka 2a232d81f6 Remove definitions of double word shift plus 32 instructions. Assembler or 
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893
 2011-12-19 19:44:09 +00:00
Akira Hatanaka c4db30e358 Remove unused predicate. 
llvm-svn: 146889
 2011-12-19 19:32:20 +00:00
Akira Hatanaka 5ee8464e48 Rename WrapperPIC. It is now used for both pic and static. 
llvm-svn: 146232
 2011-12-09 01:53:17 +00:00
Akira Hatanaka dee6c8275c Implement 64-bit support for thread local storage handling. 
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175
 2011-12-08 20:34:32 +00:00
Akira Hatanaka 4350c183d4 Modify class ReadHardware and add definition of 64-bit version of instruction 
RDHWR. 

llvm-svn: 146101
 2011-12-07 23:31:26 +00:00
Akira Hatanaka 9778e7a67c 32 to 64-bit anyext pattern. 
llvm-svn: 146097
 2011-12-07 23:21:19 +00:00
Akira Hatanaka ae378af667 32 to 64-bit zext pattern. 
llvm-svn: 146096
 2011-12-07 23:14:41 +00:00
Akira Hatanaka b2e05cb6b1 64-bit WrapperPICPat patterns. 
llvm-svn: 146086
 2011-12-07 22:11:43 +00:00
Akira Hatanaka 4a04a56a36 Fix 64-bit immediate patterns. 
llvm-svn: 146059
 2011-12-07 20:10:24 +00:00
Akira Hatanaka 20cee2eba1 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
 2011-12-05 21:26:34 +00:00
Akira Hatanaka 7b8547c4d0 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool 
nodes.

llvm-svn: 144841
 2011-11-16 22:39:56 +00:00
Akira Hatanaka 6d617ceca2 64-bit jump register instruction. 
llvm-svn: 144840
 2011-11-16 22:36:01 +00:00
Akira Hatanaka f93b3f46f8 32-to-64-bit extended load. 
llvm-svn: 144554
 2011-11-14 19:06:14 +00:00
Akira Hatanaka 5ed07c03f4 64-bit arbitrary immediate pattern. 
llvm-svn: 144448
 2011-11-12 02:25:00 +00:00
Akira Hatanaka 21cbc25bbb 64-bit atomic instructions. 
llvm-svn: 144372
 2011-11-11 04:14:30 +00:00
Akira Hatanaka 4bdfec57ba Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. 
llvm-svn: 144370
 2011-11-11 04:06:38 +00:00
Akira Hatanaka 0009dc2088 64-bit versions of jal, jalr and bal. 
llvm-svn: 144368
 2011-11-11 04:03:54 +00:00
Akira Hatanaka 2b8d1f163f Add definition of 64-bit load upper immediate. 
llvm-svn: 143994
 2011-11-07 19:10:49 +00:00
Akira Hatanaka cf7e5b0976 Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted 
when shift amount is larger than 32.

llvm-svn: 143990
 2011-11-07 19:01:49 +00:00
Akira Hatanaka 770f0646db Make the type of shift amount i32 in order to reduce the number of shift 
instruction definitions.

llvm-svn: 143989
 2011-11-07 18:59:49 +00:00
Akira Hatanaka d5c1329078 Add 64-bit to 32-bit trunc pattern. 
llvm-svn: 143988
 2011-11-07 18:57:41 +00:00
Akira Hatanaka 33fe8f908c Redefine count-leading 0s and 1s instructions. 
llvm-svn: 142216
 2011-10-17 18:26:37 +00:00
Akira Hatanaka 8c446be204 Redefine mfhi/lo and mthi/lo instructions. 
llvm-svn: 142214
 2011-10-17 18:24:15 +00:00
Akira Hatanaka 0317b65367 Redefine multiply and divide instructions. 
llvm-svn: 142211
 2011-10-17 18:21:24 +00:00
Akira Hatanaka 2736bbc09e Add definition of a base class for logical shift/rotate instructions with two 
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
 2011-10-17 18:17:58 +00:00
Akira Hatanaka 73081309c3 Add definition of a base class for logical shift/rotate immediate instructions 
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
 2011-10-17 18:06:56 +00:00
Akira Hatanaka e3f27b79dc Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. 
llvm-svn: 142205
 2011-10-17 18:01:00 +00:00
Akira Hatanaka 3261c0fa6e Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. 
llvm-svn: 141761
 2011-10-12 01:05:13 +00:00
Akira Hatanaka 8f0d549c4c Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical 
instructions with two register operands derive from it.

llvm-svn: 141742
 2011-10-11 23:38:52 +00:00
Akira Hatanaka ae5a9d6578 Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit 
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
 2011-10-11 23:05:46 +00:00
Akira Hatanaka 453ac88b56 Change the names of 64-bit logical instructions so that they match the names of 
the real instructions.

llvm-svn: 141718
 2011-10-11 21:48:01 +00:00
Akira Hatanaka 46a7994ac9 Remove redundancy in setcc patterns using multiclass. 
llvm-svn: 141715
 2011-10-11 21:40:01 +00:00
Akira Hatanaka 8c1c51045d Use sltiu instead of sltu when a register operand and immediate are compared. 
llvm-svn: 141708
 2011-10-11 20:44:43 +00:00
Akira Hatanaka 7148bce86e Add patterns for conditional branches with 64-bit register operands. 
llvm-svn: 141696
 2011-10-11 19:09:09 +00:00
Akira Hatanaka f75add6236 Add support for 64-bit set-on-less-than instructions. 
llvm-svn: 141695
 2011-10-11 18:53:46 +00:00
Akira Hatanaka 4b6ac98fcf Add support for conditional branch instructions with 64-bit register operands. 
llvm-svn: 141694
 2011-10-11 18:49:17 +00:00
Akira Hatanaka b6d72cbeb9 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
 2011-10-11 01:12:52 +00:00
Akira Hatanaka 09b23eb7bc Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.

llvm-svn: 141618
 2011-10-11 00:55:05 +00:00
Akira Hatanaka be68f3c348 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
 2011-10-11 00:27:28 +00:00
Akira Hatanaka fd2d7dcc31 Change definitions of classes LoadM and StoreM in preparation for adding support 
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
 2011-10-11 00:11:12 +00:00
Akira Hatanaka c3a6357ee3 Add support for 64-bit logical NOR. 
llvm-svn: 141029
 2011-10-03 21:23:18 +00:00
Akira Hatanaka 48a72ca0cb Add support for 64-bit count leading ones and zeros instructions. 
llvm-svn: 141028
 2011-10-03 21:16:50 +00:00
Akira Hatanaka b1538f91dc Add support for 64-bit divide instructions. 
llvm-svn: 141024
 2011-10-03 21:06:13 +00:00
Akira Hatanaka a279d9bd6a Add support for 64-bit integer multiply instructions. 
llvm-svn: 141017
 2011-10-03 20:01:11 +00:00
Akira Hatanaka cdcc74563c Add definitions of instructions which move values between 64-bit integer 
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015
 2011-10-03 19:28:44 +00:00
Akira Hatanaka 7ba8a8d656 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Akira Hatanaka 9727af7657 isCommutable should be 0 for DSUBu. 
llvm-svn: 140862
 2011-09-30 17:26:36 +00:00
Akira Hatanaka 61e256aa69 Mips64 shift instructions. 
llvm-svn: 140841
 2011-09-30 03:18:46 +00:00
Akira Hatanaka 7769a77710 Mips64 arithmetic and logical instructions with one source register and 
immediate.

llvm-svn: 140839
 2011-09-30 02:08:54 +00:00
Akira Hatanaka 36036412e2 Mips64 arithmetic and logical instructions with two source registers. 
llvm-svn: 140806
 2011-09-29 20:37:56 +00:00
Akira Hatanaka c117967b19 Mips64 predicate definitions. Patch by Liu. 
llvm-svn: 140703
 2011-09-28 17:50:27 +00:00
Akira Hatanaka 7d7ee0c3ac Add .td file. 
llvm-svn: 140446
 2011-09-24 01:40:18 +00:00