16048332f1
[mips] Fix definition of mfhi and mflo instructions to read from the whole
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accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
llvm-svn: 192119
2013-10-07 18:49:46 +00:00
3671a5441a
Support for microMIPS DIV instructions.
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llvm-svn: 190745
2013-09-14 07:15:21 +00:00
ab85278137
Support for misc microMIPS instructions.
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llvm-svn: 190744
2013-09-14 06:49:25 +00:00
3121353c99
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
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into a 5-bit or 6-bit field.
llvm-svn: 190226
2013-09-07 00:02:02 +00:00
b936da159e
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
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llvm-svn: 190154
2013-09-06 13:08:00 +00:00
457ba56b05
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
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llvm-svn: 190152
2013-09-06 12:53:21 +00:00
e0fbb44a48
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
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llvm-svn: 190148
2013-09-06 12:41:17 +00:00
dde3d582a2
This patch adds support for microMIPS disassembler and disassembler make check tests.
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llvm-svn: 190144
2013-09-06 12:30:36 +00:00
6781fc1648
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
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load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
llvm-svn: 188830
2013-08-20 21:08:22 +00:00
a43b56d9af
[mips] Guard micromips instructions with predicate InMicroMips. Also, fix
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assembler predicate HasStdEnd so that it is false when the target is micromips.
llvm-svn: 188824
2013-08-20 20:46:51 +00:00
8002a3f6d8
[mips] Rename HIRegs and LORegs.
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llvm-svn: 188341
2013-08-14 00:47:08 +00:00
9770097727
[Mips] Support for unaligned load/store microMips instructions
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This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
llvm-svn: 188312
2013-08-13 20:19:16 +00:00
13e6ccf341
[mips] Rename register classes CPURegs and CPU64Regs.
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llvm-svn: 187832
2013-08-06 23:08:38 +00:00
34a32c0b87
[mips] Replace usages of register classes with register operands. Also, remove
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unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
llvm-svn: 187821
2013-08-06 22:20:40 +00:00
f8fff213d5
[mips] Define instruction itineraries IIArith and IILogic.
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No functionality change.
llvm-svn: 187468
2013-07-31 00:55:34 +00:00
59817110ff
Mips td file formatting: white space and long lines
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llvm-svn: 182047
2013-05-16 20:08:49 +00:00
f0aa6c9101
[mips] Add definitions of micromips load and store instructions.
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Patch by Zoran Jovanovic.
llvm-svn: 180241
2013-04-25 01:21:25 +00:00
cd9b74a599
[mips] Add definitions of micromips shift instructions.
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Patch by Zoran Jovanovic.
llvm-svn: 180238
2013-04-25 01:11:15 +00:00
be6a818fd4
[mips] First patch which adds support for micromips.
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This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.
Patch by Zoran Jovanovic.
llvm-svn: 179873
2013-04-19 19:03:11 +00:00
Akira Hatanaka