cb8b40b08d
[mips][msa] Direct Object Emission for 3RF instructions.
...
Patch by Matheus Almeida
llvm-svn: 191461
2013-09-26 21:31:43 +00:00
142ec8283d
[mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06).
...
This does not affect any of the existing output.
Patch by Matheus Almeida
llvm-svn: 191460
2013-09-26 21:18:57 +00:00
3eb663b037
[mips][msa] Direct Object Emission for 3R instructions.
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This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
Patch by Matheus Almeida
llvm-svn: 191415
2013-09-26 00:09:46 +00:00
77551abef4
[mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06).
...
Internal changes only.
Patch by Matheus Almeida
llvm-svn: 191414
2013-09-26 00:02:44 +00:00
3381298227
[mips][msa] Direct Object Emission for 2RF instructions.
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Patch by Matheus Almeida
llvm-svn: 191413
2013-09-25 23:56:25 +00:00
5dc8ac92b9
[mips][msa] Direct Object Emission support for the MSA instruction set.
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In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.
Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).
Patch by Matheus Almeida
llvm-svn: 191412
2013-09-25 23:50:44 +00:00
56c681eb7f
[mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06).
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This only changes internal encodings and doesn't affect output.
Patch by Matheus Almeida
llvm-svn: 191411
2013-09-25 23:42:03 +00:00
fae5f2a9c9
[mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics)
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llvm-svn: 191306
2013-09-24 14:53:25 +00:00
2ed228b29b
[mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics)
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llvm-svn: 191304
2013-09-24 14:36:12 +00:00
2630718ae8
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)
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llvm-svn: 191302
2013-09-24 14:20:00 +00:00
e508704b52
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)
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llvm-svn: 191301
2013-09-24 14:02:15 +00:00
f49dd82e06
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.
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Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp
This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).
There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.
compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.
llvm-svn: 191299
2013-09-24 13:33:07 +00:00
4f3ff1b9e8
[mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics)
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This covers the case where fmax_a can be used to implement ISD::FABS.
llvm-svn: 191296
2013-09-24 13:02:08 +00:00
5a942e6fd0
[mips][msa] Line wrapping.
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No functional change.
llvm-svn: 191295
2013-09-24 12:45:36 +00:00
bfc39cedf2
[mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics)
...
llvm-svn: 191293
2013-09-24 12:32:47 +00:00
3ce56622c8
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics)
...
llvm-svn: 191291
2013-09-24 12:18:31 +00:00
e1d2435543
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics)
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This required correcting the definition of the bsel and bseli intrinsics.
llvm-svn: 191290
2013-09-24 12:04:44 +00:00
fd538dc745
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics)
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MIPS SelectionDAG changes:
* Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask.
llvm-svn: 191286
2013-09-24 10:46:19 +00:00
cba1922915
[mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics)
...
llvm-svn: 191285
2013-09-24 10:28:18 +00:00
86d0c8d751
[mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics)
...
llvm-svn: 191203
2013-09-23 14:29:55 +00:00
a4c8f3a7b0
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)
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Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
operation and implemented the DAG combines necessary to fold sign/zero
extends into the extract.
llvm-svn: 191199
2013-09-23 14:03:12 +00:00
766cb697a8
[mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)
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llvm-svn: 191198
2013-09-23 13:40:21 +00:00
f7456c78f0
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)
...
llvm-svn: 191195
2013-09-23 13:22:24 +00:00
8ca81e484e
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics)
...
llvm-svn: 191194
2013-09-23 12:57:42 +00:00
7a289d0e39
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)
...
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).
Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
This is a special case of BUILD_VECTOR that covers the case the
BUILD_VECTOR is a splat operation.
* Added VSPLATD
This is a special case of VSPLAT that handles the cases when v2i64 is legal
llvm-svn: 191191
2013-09-23 12:02:46 +00:00
fbcb582942
[mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics)
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llvm-svn: 190518
2013-09-11 11:58:30 +00:00
f5bd937bc4
[mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics)
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llvm-svn: 190512
2013-09-11 10:51:30 +00:00
607952bdad
[mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
...
llvm-svn: 190509
2013-09-11 10:38:58 +00:00
fa5ab1c856
[mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)
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The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.
llvm-svn: 190507
2013-09-11 10:28:16 +00:00
cb2929c239
[mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
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The elements of the operands should be half the width of the elements of
the result.
llvm-svn: 190505
2013-09-11 09:59:17 +00:00
f561730af8
[mips][msa] Removed unsupported dot product instructions (dotp_[su].b)
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The dotp_[su].b instructions never existed in any revision of the MSA spec.
llvm-svn: 190398
2013-09-10 09:51:43 +00:00
3121353c99
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
...
into a 5-bit or 6-bit field.
llvm-svn: 190226
2013-09-07 00:02:02 +00:00
af7f805b96
[mips][msa] Indentation
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llvm-svn: 190156
2013-09-06 13:25:06 +00:00
636f72fc08
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
...
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.
llvm-svn: 190155
2013-09-06 13:15:05 +00:00
563e5eabe5
[mips][msa] Made the operand register sets optional for the VEC formats
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Their default is to be the same as the result register set.
No functional change
llvm-svn: 190153
2013-09-06 13:01:47 +00:00
41fb2c0d0e
[mips][msa] Made the operand register sets optional for the ELM_INSVE formats
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Their default is to be the same as the result register set.
No functional change
llvm-svn: 190151
2013-09-06 12:50:52 +00:00
fa1b0fa77e
[mips][msa] Made the operand register sets optional for the 3RF_4RF format
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Their default is to be the same as the result register set.
No functional change
llvm-svn: 190150
2013-09-06 12:44:13 +00:00
d719f5281c
[mips][msa] Made the operand register sets optional for the 3RF formats
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190146
2013-09-06 12:32:57 +00:00
b2b7c0a044
[mips][msa] Made the operand register sets optional for the 3R_4R format
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190145
2013-09-06 12:30:43 +00:00
2322f5d090
[mips][msa] Made the operand register sets optional for the 2RF format
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190143
2013-09-06 12:28:13 +00:00
9148218cbe
[mips][msa] Made the operand register sets optional for the I8 format
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Their default is to be the same as the result register set.
No functional change
llvm-svn: 190142
2013-09-06 12:25:47 +00:00
92c40a5796
[mips][msa] Made the operand register sets optional for the I5 and SI5 formats
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Their default is to be the same as the result register set.
No functional change
llvm-svn: 190141
2013-09-06 12:23:19 +00:00
13d5e2f376
[mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
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Their default is to be the same as the result register set.
No functional change
llvm-svn: 190140
2013-09-06 12:10:24 +00:00
63b97d5ae5
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
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No functional change
llvm-svn: 190134
2013-09-06 11:01:38 +00:00
02a3007608
[mips][msa] Made the operand register sets optional for the 3R format
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190133
2013-09-06 10:59:24 +00:00
db12ab7b7c
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
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No functional change
llvm-svn: 190131
2013-09-06 10:55:15 +00:00
ce09d07824
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
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These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.
Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.
llvm-svn: 189478
2013-08-28 12:14:50 +00:00
e6ed5b72f1
[mips][msa] Added load/store intrinsics.
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llvm-svn: 189476
2013-08-28 12:04:29 +00:00
ba9c8505fb
[mips][msa] Added move.v
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llvm-svn: 189471
2013-08-28 10:44:47 +00:00
f9aa1d1902
[mips][msa] Added cfcmsa, and ctcmsa
...
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.
llvm-svn: 189468
2013-08-28 10:26:24 +00:00
0dc0dd464b
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri
...
llvm-svn: 189467
2013-08-28 10:12:09 +00:00
70835f6025
[mips][msa] Added bitconverts for vector types for big and little-endian
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llvm-svn: 189330
2013-08-27 09:40:30 +00:00
3c9a0ad444
[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.
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llvm-svn: 189095
2013-08-23 10:10:13 +00:00
4260527f5f
[mips][msa] Removed fcge, fcgt, fsge, fsgt
...
These instructions were present in a draft spec but were removed before
publication.
llvm-svn: 188782
2013-08-20 09:41:47 +00:00
f2a0f1d133
[mips][msa] Added insve
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llvm-svn: 188777
2013-08-20 09:22:54 +00:00
869bdad93a
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
...
llvm-svn: 188767
2013-08-20 08:38:21 +00:00
6b32f892f2
Reverted test commit (r188556)
...
llvm-svn: 188557
2013-08-16 15:27:12 +00:00
7a2c9bc894
Test commit. Just a blank line
...
llvm-svn: 188556
2013-08-16 15:26:36 +00:00
d12e837f05
[Mips][msa] Added the simple builtins (madd_q to xori)
...
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori
Patch by Daniel Sanders
llvm-svn: 188460
2013-08-15 14:22:07 +00:00
b95ee69163
[Mips][msa] Added the simple builtins (fadd to ftq)
...
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq
Patch by Daniel Sanders
llvm-svn: 188458
2013-08-15 13:45:36 +00:00
babdcc8c2c
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
...
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 12:24:57 +00:00
3a2c2d42b8
[Mips][msa] Added initial MSA support.
...
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
llvm-svn: 188313
2013-08-13 20:54:07 +00:00
Jack Carter