fcc9e6848a
If we have an undef mask our Elt will be -1 for our access, handle
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this by using an undef as a pointer.
Fixes rdar://8625016
llvm-svn: 118164
2010-11-03 09:36:40 +00:00
8740ee3637
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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llvm-svn: 118160
2010-11-03 06:34:55 +00:00
6f36042557
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
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llvm-svn: 118152
2010-11-03 05:14:24 +00:00
6552a109bb
Put the PC encoding in the correct bit position.
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llvm-svn: 118151
2010-11-03 04:57:44 +00:00
c63d846ad6
Invert these branches by default, it makes assembly comparisons a little
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easier to read.
llvm-svn: 118148
2010-11-03 04:29:11 +00:00
e84eb99cbb
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
68fb004616
Fix DAGCombiner to avoid going into an infinite loop when it
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encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.
llvm-svn: 118143
2010-11-03 01:47:46 +00:00
fd96701456
Remove unused function.
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llvm-svn: 118141
2010-11-03 01:35:15 +00:00
e7f7de95e0
Remove the no longer used 'Modifier' optional operand to the ARM
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printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
2010-11-03 01:11:15 +00:00
50ba3c09bf
Remove unused function.
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llvm-svn: 118139
2010-11-03 01:07:48 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
debf9c502a
Two sets of changes. Sorry they are intermingled.
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1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
llvm-svn: 118135
2010-11-03 00:45:17 +00:00
634ab6c2b7
Modify scheduling itineraries to correct instruction latencies (not operand
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latencies) of loads.
llvm-svn: 118134
2010-11-03 00:40:22 +00:00
0baea2aa1b
Print an error as one big string instead of breaking it up.
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llvm-svn: 118130
2010-11-03 00:24:33 +00:00
a3bb142db6
Delete unused variables.
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llvm-svn: 118128
2010-11-03 00:09:12 +00:00
ecc4d73498
Remove several unhelpful checks for isValid from sys::Path.
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llvm-svn: 118127
2010-11-03 00:01:23 +00:00
1e43892e4b
Make sure we're only storing a single bit here.
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llvm-svn: 118126
2010-11-02 23:59:09 +00:00
9c9bfb6870
per a suggestion by Frits van Bommel, mark all MBlaze Pseudo
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instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.
llvm-svn: 118125
2010-11-02 23:57:05 +00:00
0ebd1fd594
Revert r118097 to fix buildbots.
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llvm-svn: 118121
2010-11-02 23:47:29 +00:00
cc5dce89d4
Completely reject instructions that have an operand in their
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ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
31a7eb40c1
Let the -inline-threshold command line argument take precedence over the
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threshold given to createFunctionInliningPass().
Both opt -O3 and clang would silently ignore the -inline-threshold option.
llvm-svn: 118117
2010-11-02 23:40:26 +00:00
c0a8bee4b0
Don't try to enforce MAXPATHLEN in sys::Path for Unix. OS's can check
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limits on their own.
llvm-svn: 118113
2010-11-02 23:19:55 +00:00
a8b6315cd7
Simplify.
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llvm-svn: 118110
2010-11-02 23:16:26 +00:00
6e05d6c218
Fix a copy+pasto.
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llvm-svn: 118106
2010-11-02 22:56:51 +00:00
a47bfef1bf
Avoid manipulating paths in fixed-sized arrays.
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llvm-svn: 118105
2010-11-02 22:55:34 +00:00
f9eebb58b9
Obsessive formatting changes. No functionality impact.
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llvm-svn: 118103
2010-11-02 22:53:11 +00:00
32d51fa0b5
Simplify this code.
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llvm-svn: 118102
2010-11-02 22:50:10 +00:00
23436b6530
Omit unused parameter name.
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llvm-svn: 118099
2010-11-02 22:46:04 +00:00
91da9abbee
Simplify the EncodeInstruction method now that a lot of the special case stuff
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is handled with the MC encoder.
llvm-svn: 118098
2010-11-02 22:44:12 +00:00
7c30390277
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
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llvm-svn: 118097
2010-11-02 22:41:42 +00:00
f6e13ceb2b
Use '\0' instead of 0 for nul character constants.
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llvm-svn: 118096
2010-11-02 22:41:19 +00:00
603bd8f54c
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
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with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
2010-11-02 22:31:46 +00:00
a4b63e19d2
Rename encoder methods to match naming convention.
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llvm-svn: 118093
2010-11-02 22:28:01 +00:00
15977afb02
mark a few codegenonly instructions.
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llvm-svn: 118092
2010-11-02 22:26:33 +00:00
7282901079
appendSuffix: don't append a dot when the suffix is empty.
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Additionally, move the implementation of appendSuffix to Path.cpp: it is
platform-independent.
llvm-svn: 118089
2010-11-02 22:18:37 +00:00
4fb337560c
Revert r118057, this is better fixed in appendSuffix itself.
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llvm-svn: 118088
2010-11-02 22:18:28 +00:00
dec87e10fd
Provide correct encodings for the remaining vst variants that we currently generate.
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llvm-svn: 118087
2010-11-02 22:18:18 +00:00
44e24e5403
Eliminate some temporary std::strings.
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llvm-svn: 118086
2010-11-02 22:07:47 +00:00
adf88d4c5f
Tentative encodings for the "single element from one lane" variant of vst1.
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llvm-svn: 118084
2010-11-02 21:54:45 +00:00
b95618cfe0
Add correct encodings for basic variants for vst3 and vst4.
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llvm-svn: 118082
2010-11-02 21:47:03 +00:00
f8343f87e7
Do relaxations with FT_Org fragments. Fixes the FIXME:
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// FIXME: We should compute this sooner, we don't want to recurse here, and
// we would like to be more functional.
In MCAssembler::ComputeFragmentSize.
llvm-svn: 118080
2010-11-02 21:38:23 +00:00
d80b29d6f7
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
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llvm-svn: 118069
2010-11-02 21:18:25 +00:00
fa08e1e277
Add correct encodings for the basic variants for vst2.
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llvm-svn: 118068
2010-11-02 21:16:58 +00:00
87c62e54e6
Add correct encodings for the basic form of vst1.
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llvm-svn: 118067
2010-11-02 21:06:06 +00:00
bba85850e3
Micro-optimize.
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llvm-svn: 118058
2010-11-02 20:52:47 +00:00
35b2013bf8
Don't append a dot on platforms which don't use exe suffixes.
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llvm-svn: 118057
2010-11-02 20:49:48 +00:00
0ddd57451e
llvmc: Fix tool finding logic.
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llvm-svn: 118056
2010-11-02 20:47:41 +00:00
9f20daf3b4
Factor out a common encoding class for loads and stores with a lane parameter.
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llvm-svn: 118055
2010-11-02 20:47:39 +00:00
415c551459
Fix DIType verifier. The element 3 is DIFile now.
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llvm-svn: 118054
2010-11-02 20:41:13 +00:00
a83859539f
Add correct encodings for the rest of the vld instructions that we generate.
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llvm-svn: 118053
2010-11-02 20:40:59 +00:00
Eric Christopher