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310 Commits

Author SHA1 Message Date
Michael Zuckerman c4d054fa4a [LLVM][AVX512] PSRLWI Chnage imm8 to int 
Differential Revision: http://reviews.llvm.org/D17753

llvm-svn: 262592
 2016-03-03 08:54:05 +00:00
Michael Zuckerman 927fdaee88 [LLVM][AVX512]PSRAWI Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17705

llvm-svn: 262480
 2016-03-02 12:05:07 +00:00
Michael Zuckerman 433b241570 [LLVM][AVX512] PSRL{DI|QI} Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17713

llvm-svn: 262353
 2016-03-01 17:46:32 +00:00
Michael Zuckerman 7878888690 [AVX512][PSRAQ][PSRAD] Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17692

llvm-svn: 262320
 2016-03-01 11:36:23 +00:00
Michael Zuckerman 96836fc81c [AVX512][PSLLW ][PSLLV] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17684

llvm-svn: 262176
 2016-02-28 07:32:10 +00:00
Simon Pilgrim 3b42ca0760 Strip trailing whitespace. NFCI. 
llvm-svn: 262131
 2016-02-27 11:49:16 +00:00
Michael Zuckerman a1f2d27da2 [LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17538

llvm-svn: 261725
 2016-02-24 08:39:05 +00:00
Michael Zuckerman 724dc3b20c [AVX512][PRORQ][PRORD] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17024

llvm-svn: 261198
 2016-02-18 09:52:12 +00:00
Ahmed Bougacha f3cccab1e0 [X86] Remove the now-unused X86ISD::PSIGN. NFC. 
llvm-svn: 261025
 2016-02-16 22:14:12 +00:00
Michael Zuckerman 529c27f408 [AVX512][PROLQ][PROLD] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D16983

llvm-svn: 260101
 2016-02-08 15:13:32 +00:00
Asaf Badouh ad5c3fc47d [X86][AVX512] add intrinsics of Scalar FP to integer conversion with rounding mode 
Differential Revision: http://reviews.llvm.org/D16629

llvm-svn: 260033
 2016-02-07 14:59:13 +00:00
Igor Breger 0aeda37464 AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation. 
Differential Revision: http://reviews.llvm.org/D16813

llvm-svn: 260024
 2016-02-07 08:30:50 +00:00
Michael Zuckerman 7d73360479 [AVX512] add vfmadd132ss and vfmadd132sd Intrinsic 
Differential Revision: http://reviews.llvm.org/D16589

llvm-svn: 259789
 2016-02-04 14:41:08 +00:00
Asaf Badouh 5a3a0231f4 [X86][AVX512VBMI] add encoding and intrinsics for Multishift 
Differential Revision: http://reviews.llvm.org/D16399

llvm-svn: 259363
 2016-02-01 15:48:21 +00:00
Asaf Badouh 42852d99e7 [X86][AVX512] small fix in ptestm intrinsics 
move ptestm{q|d} intrinsics from patterns form (in td file) to the intrinsics table

Differential Revision: http://reviews.llvm.org/D16633

llvm-svn: 259029
 2016-01-28 08:33:22 +00:00
Benjamin Kramer 391be792f2 One more batch of self-containing headers. 
llvm-svn: 258974
 2016-01-27 19:29:56 +00:00
Reid Kleckner 86ff2689a5 Sort intrinsics by LLVM intrinsic name, rather than tablegen def name 
Step one towards using a simple binary search to lookup intrinsic IDs
instead of our crazy table generated switch+memcmp+startswith code that
makes Function.cpp take about a minute to compile.  See PR24785 and
PR11951 for why we should do this.

The X86 backend contains tables that need to be sorted on intrinsic ID,
so reorder those.

llvm-svn: 258757
 2016-01-26 00:55:00 +00:00
Michael Zuckerman 1bd7f993fc [AVX512] Adding PTESTNMB/D/W/Q instruction 
Differential Revision: http://reviews.llvm.org/D16520

llvm-svn: 258688
 2016-01-25 14:43:23 +00:00
Michael Zuckerman 19670d479a [AVX512] Adding PTESTMB/W/D/Q instruction 
Differential Revision: http://reviews.llvm.org/D16519

llvm-svn: 258686
 2016-01-25 13:27:32 +00:00
Asaf Badouh 655822ab7e [X86][IFMA] adding intrinsics and encoding for multiply and add of unsigned 52bit integer 
VPMADD52LUQ - Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators
 VPMADD52HUQ - Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators

Differential Revision: http://reviews.llvm.org/D16407

llvm-svn: 258680
 2016-01-25 11:14:24 +00:00
Igor Breger 1e5bafbc82 AVX512: VMOVDQU8/16/32/64 (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16137

llvm-svn: 258657
 2016-01-24 08:04:33 +00:00
Igor Breger 7a000f5bb2 AVX512: Masked move intrinsic implementation. 
Implemented intrinsic for the follow instructions (reg move) : VMOVDQU8/16, VMOVDQA32/64, VMOVAPS/PD.

Differential Revision: http://reviews.llvm.org/D16316

llvm-svn: 258398
 2016-01-21 14:18:11 +00:00
Michael Zuckerman 21a30a42a9 [AVX512] Adding VPERMT2B and VPERMI2B Intrinsics 
Differential Revision: http://reviews.llvm.org/D16398

llvm-svn: 258397
 2016-01-21 13:36:01 +00:00
Michael Zuckerman 65c40afb03 [AVX512] Adding VPERMB Intrinsics 
Differential Revision: http://reviews.llvm.org/D16296

llvm-svn: 258316
 2016-01-20 15:24:56 +00:00
Igor Breger d3341f5021 AVX512: Store (MOVNTPD, MOVNTPS, MOVNTDQ) using non-temporal hint intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16350

llvm-svn: 258309
 2016-01-20 13:11:47 +00:00
Asaf Badouh d4a0d9a78c [X86][AVX512]fix dag & add intrinsics for fixupimm 
cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics

Differential Revision: http://reviews.llvm.org/D16313

llvm-svn: 258124
 2016-01-19 14:21:39 +00:00
Igor Breger 239fda676c AVX512: Masked store intrinsic implementation. 
Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD.

Differential Revision: http://reviews.llvm.org/D16271

llvm-svn: 258047
 2016-01-18 13:52:57 +00:00
Michael Zuckerman ac1b238b0a [AVX512] Adding VPERMW/D/Q VPERMPS/D Intrinsics 
Differential Revision: http://reviews.llvm.org/D16189

llvm-svn: 258008
 2016-01-17 11:33:29 +00:00
Michael Zuckerman ede597c753 [AVX512] Adding VPERMQ VPERMPD Intrinsics 
Differential Revision: http://reviews.llvm.org/D16194

llvm-svn: 258006
 2016-01-17 08:32:14 +00:00
Igor Breger fc96331d88 AVX512: VMOVDQA32/64 (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16142

llvm-svn: 257749
 2016-01-14 07:56:04 +00:00
Michael Zuckerman 0e31b22487 [AVX512] Adding PMOVSXBD/W/Q , PMOVZSDQ and PMOVZSWD/Q Intrinsics . 
Differential Revision: http://reviews.llvm.org/D16111 

llvm-svn: 257604
 2016-01-13 14:59:19 +00:00
Michael Zuckerman 43cea85db9 [AVX512] Adding PMOVZXBD/W/Q , PMOVZXDQ and PMOVZXWD/Q Intrinsics 
Differential Revision:http://reviews.llvm.org/D16071

llvm-svn: 257601
 2016-01-13 14:25:21 +00:00
Michael Zuckerman 298a680c80 [AVX512] adding PRORQ , PRORD , PRORLVQ and PRORLVD Intrinsics 
Differential Revision: http://reviews.llvm.org/D16052

llvm-svn: 257594
 2016-01-13 12:39:33 +00:00
Michael Zuckerman 2ddcbcf464 [AVX512] adding PROLQ and PROLD Intrinsics 
Differential Revision: http://reviews.llvm.org/D16048

llvm-svn: 257523
 2016-01-12 21:19:17 +00:00
Igor Breger ea8e8e9f97 AVX512: VPMOVAPS/PD and VPMOVUPS/PD (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16042

llvm-svn: 257463
 2016-01-12 10:02:32 +00:00
Michael Zuckerman 885f61c534 [AVX512] add PRORVQ and PRORVD Intrinsic 
Differential Revision:http://reviews.llvm.org/D15955

llvm-svn: 257283
 2016-01-10 09:16:41 +00:00
Michael Zuckerman 3aca221b31 [AVX512] add PSLLW and PSLLV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15889

llvm-svn: 257070
 2016-01-07 16:02:51 +00:00
Michael Zuckerman 354152d590 [AVX512] add PSRAV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15856

llvm-svn: 257063
 2016-01-07 14:42:20 +00:00
Michael Zuckerman a6df006b50 [AVX512] add PSHUFHW and PSHUFLW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15925

llvm-svn: 257056
 2016-01-07 12:35:43 +00:00
Michael Zuckerman 4a1566827d [AVX512] add PSHUFD Intrinsic 
Differential Revision: http://reviews.llvm.org/D15934

llvm-svn: 257044
 2016-01-07 09:24:12 +00:00
Michael Zuckerman 5cbae95916 [AVX512] add PSLLD and PSLLQ Intrinsic 
Differential Revision: http://reviews.llvm.org/D15885

llvm-svn: 256840
 2016-01-05 15:17:39 +00:00
Michael Zuckerman cf0b6db9ef [AVX512] add PSRAD and PSRAQ Intrinsic 
Differential Revision: http://reviews.llvm.org/D15851

llvm-svn: 256754
 2016-01-04 13:45:45 +00:00
Michael Zuckerman 000fca44a8 [AVX512] add PSRAW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15850

llvm-svn: 256751
 2016-01-04 12:50:36 +00:00
Michael Zuckerman 068bc2f219 [AVX512] add PSRLV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15838

llvm-svn: 256747
 2016-01-04 11:39:06 +00:00
Michael Zuckerman 0dc468880d [AVX512] add PSRLQ and PSRLD Intrinsic 
Differential Revision: http://reviews.llvm.org/D15770

llvm-svn: 256673
 2015-12-31 15:22:04 +00:00
Michael Zuckerman 80821ee77c [AVX512] add PSRLW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15751

llvm-svn: 256558
 2015-12-29 13:04:35 +00:00
Asaf Badouh fba562004b [X86][AVX512] Lower broadcast sub vector to vector inrtrinsics 
lower broadcast<type>x<vector> to shuffles.
 there are two cases:
1.src is 128 bits and dest is 512 bits: in this case we will lower it to shuffle with imm = 0.
2.src is 256 bit and dest is 512 bits: in this case we will lower it to shuffle with imm = 01000100b (0x44) that way we will broadcast the 256bit source: ymm[0,1,2,3] => zmm[0,1,2,3,0,1,2,3] then it will mask it with the passthru value (in case it's mask op).



Differential Revision: http://reviews.llvm.org/D15790

llvm-svn: 256490
 2015-12-28 08:26:26 +00:00
Asaf Badouh 5546f51011 [X86][AVX512] add fp scalar broadcast intrinsics 
Differential Revision: http://reviews.llvm.org/D15790

llvm-svn: 256489
 2015-12-28 08:09:25 +00:00
Igor Breger 756c289dd8 AVX512: Change VPMOVB2M DAG lowering , use CVT2MASK node instead TRUNCATE. 
Fix TRUNCATE lowering vector to vector i1, use LSB and not MSB.
Implement VPMOVB/W/D/Q2M intrinsic.

Differential Revision: http://reviews.llvm.org/D15675

llvm-svn: 256470
 2015-12-27 13:56:16 +00:00
Igor Breger 268f6f53c5 AVX512: VPMOVM2B/W/D/Q intrinsic implementation. 
Differential Revision: http://reviews.llvm.org//D15747

llvm-svn: 256364
 2015-12-24 07:11:53 +00:00
Asaf Badouh 13ffa4bf7c [X86][AVX512] Add rcp14 and rsqrt14 intrinsics 
Differential Revision: http://reviews.llvm.org/D15414

llvm-svn: 256237
 2015-12-22 11:40:04 +00:00
Igor Breger 3ab6f17530 AVX-512: implement kunpck intrinsics. 
Differential Revision: http://reviews.llvm.org/D14821

llvm-svn: 254908
 2015-12-07 13:25:18 +00:00
Asaf Badouh 41ecf460fa [X86][AVX512] add vmovss/sd missing encoding 
Differential Revision: http://reviews.llvm.org/D14701

llvm-svn: 254875
 2015-12-06 13:26:56 +00:00
Asaf Badouh 2489f350c0 [X86][AVX512] add comi with Sae 
add builtin_ia32_vcomisd and builtin_ia32_vcomisd

Differential Revision: http://reviews.llvm.org/D14331

llvm-svn: 254493
 2015-12-02 08:17:51 +00:00
Craig Topper fbde7aa13a [X86] Remove duplicate entries from intrinsics tables and add asserts to verify there are no others. 
llvm-svn: 254274
 2015-11-29 23:18:32 +00:00
Craig Topper 0009656335 [X86] Split ISD node for Vfpclass and Vfpclasss so that we can write strong type constraints for each that don't cause ambiguous isel. 
llvm-svn: 254172
 2015-11-26 19:41:34 +00:00
Cong Hou db6220f84d [X86] Fix several issues related to X86's psadbw instruction. 
This patch fixes the following issues:

1. Fix the return type of X86psadbw: it should not be the same type of inputs.
   For vNi8 inputs the output should be vMi64, where M = N/8.
2. Fix the return type of int_x86_avx512_psad_bw_512 accordingly.
3. Fix the definiton of PSADBW, VPSADBW, and VPSADBWY accordingly.
4. Adjust the return type when building a DAG node of X86ISD::PSADBW type.
5. Update related tests.


Differential revision: http://reviews.llvm.org/D14897

llvm-svn: 254010
 2015-11-24 19:51:26 +00:00
Cong Hou bed60d35ed [X86][SSE] Detect AVG pattern during instruction combine for SSE2/AVX2/AVX512BW. 
This patch detects the AVG pattern in vectorized code, which is simply
c = (a + b + 1) / 2, where a, b, and c have the same type which are vectors of
either unsigned i8 or unsigned i16. In the IR, i8/i16 will be promoted to
i32 before any arithmetic operations. The following IR shows such an example:

%1 = zext <N x i8> %a to <N x i32>
%2 = zext <N x i8> %b to <N x i32>
%3 = add nuw nsw <N x i32> %1, <i32 1 x N>
%4 = add nuw nsw <N x i32> %3, %2
%5 = lshr <N x i32> %N, <i32 1 x N>
%6 = trunc <N x i32> %5 to <N x i8>

and with this patch it will be converted to a X86ISD::AVG instruction.

The pattern recognition is done when combining instructions just before type
legalization during instruction selection. We do it here because after type
legalization, it is much more difficult to do pattern recognition based
on many instructions that are doing type conversions. Therefore, for
target-specific instructions (like X86ISD::AVG), we need to take care of type
legalization by ourselves. However, as X86ISD::AVG behaves similarly to
ISD::ADD, I am wondering if there is a way to legalize operands and result
types of X86ISD::AVG together with ISD::ADD. It seems that the current design
doesn't support this idea.

Tests are added for SSE2, AVX2, and AVX512BW and both i8 and i16 types of
variant vector sizes.


Differential revision: http://reviews.llvm.org/D14761

llvm-svn: 253952
 2015-11-24 05:44:19 +00:00
Igor Breger 1f78296869 AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14702

llvm-svn: 253548
 2015-11-19 08:26:56 +00:00
Asaf Badouh 0d957b8b09 [X86][AVX512CD] add mask broadcast intrinsics 
Differential Revision: http://reviews.llvm.org/D14573

llvm-svn: 253450
 2015-11-18 09:42:45 +00:00
Igor Breger 24cab0fa06 AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14322

llvm-svn: 253185
 2015-11-16 07:22:00 +00:00
Igor Breger 3ff8ef9eb7 Revert r253160. 
It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON.

llvm-svn: 253163
 2015-11-15 12:19:11 +00:00
Igor Breger aa40ddd3ba AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14322

llvm-svn: 253160
 2015-11-15 07:23:13 +00:00
Asaf Badouh f99c054ebc revert rev. 252153 due to build failure on ubuntu 
[X86][AVX512] add comi with Sae

llvm-svn: 252154
 2015-11-05 08:55:54 +00:00
Asaf Badouh 7fdabf0a35 [X86][AVX512] add comi with Sae 
add builtin_ia32_vcomisd and builtin_ia32_vcomisd

Differential Revision: http://reviews.llvm.org/D14331

llvm-svn: 252153
 2015-11-05 08:45:06 +00:00
Igor Breger fa798a9dbb AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and VBROADCASTF32x2 instructions. 
Differential Revision: http://reviews.llvm.org/D14216

llvm-svn: 251781
 2015-11-02 07:39:36 +00:00
Benjamin Kramer 4e4ca38bcf Remove CRLF line endings. 
llvm-svn: 251594
 2015-10-29 02:33:05 +00:00
Asaf Badouh c7cb880669 [X86][AVX512] [X86][AVX512] add convert float to half 
convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem).

Differential Revision: http://reviews.llvm.org/D14113

llvm-svn: 251409
 2015-10-27 15:37:17 +00:00
Asaf Badouh 7c52245660 [X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versions 
Differential Revision: http://reviews.llvm.org/D13945

llvm-svn: 251018
 2015-10-22 14:01:16 +00:00
Igor Breger 21296d230a AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions. 
Differential Revision: http://reviews.llvm.org/D13884

llvm-svn: 250819
 2015-10-20 11:56:42 +00:00
Benjamin Kramer 335332329b Remove CRLF newlines. NFC. 
llvm-svn: 250698
 2015-10-19 13:05:25 +00:00
Asaf Badouh 696e8e0bb7 [X86][AVX512DQ] add scalar fpclass 
Differential Revision: http://reviews.llvm.org/D13769

llvm-svn: 250650
 2015-10-18 11:04:38 +00:00
Simon Pilgrim 86c5e85e84 [X86][XOP] Add VPROT instruction opcodes 
Added X86ISD opcodes for VPROT vector rotate by variable and by immediate.

llvm-svn: 250620
 2015-10-17 19:04:24 +00:00
Igor Breger b4bb190eed AVX512: Implemented encoding and intrinsics for vpternlogd/q. 
Differential Revision: http://reviews.llvm.org/D13768

llvm-svn: 250396
 2015-10-15 12:33:24 +00:00
Simon Pilgrim 52d47e5704 [X86][XOP] Added support for the lowering of 128-bit vector integer comparisons to XOP PCOM/PCOMU instructions. 
The XOP vector integer comparisons can deal with all signed/unsigned comparison cases directly and can be easily commuted as well (D7646).

llvm-svn: 249976
 2015-10-11 14:15:17 +00:00
Igor Breger 78741a1b1e AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12690

llvm-svn: 249261
 2015-10-04 07:20:41 +00:00
Simon Pilgrim 3d11c994f7 [X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions 
The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes.

Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases.

Differential Revision: http://reviews.llvm.org/D8690

llvm-svn: 248878
 2015-09-30 08:17:50 +00:00
Simon Pilgrim 9cb018b6b6 [X86][SSE] Replace 128-bit SSE41 PMOVSX intrinsics with native IR 
This patches removes the x86.sse41.pmovsx* intrinsics, provides a suitable upgrade path and updates relevant tests to sign extend a subvector instead.

LLVM counterpart to D12835

Differential Revision: http://reviews.llvm.org/D13002

llvm-svn: 248368
 2015-09-23 08:48:33 +00:00
Asaf Badouh eaf2da14bf [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP 
Differential Revision: http://reviews.llvm.org/D12524

llvm-svn: 248147
 2015-09-21 10:23:53 +00:00
Igor Breger b7e1f9d680 AVX512: Implemented encoding and intrinsics for vcmpss/sd. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12593

llvm-svn: 248121
 2015-09-20 15:15:10 +00:00
Asaf Badouh 2744d21fb8 [X86][AVX512] extend support in Scalar conversion 
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics

Differential Revision: http://reviews.llvm.org/D12665

llvm-svn: 248117
 2015-09-20 14:31:19 +00:00
Igor Breger 4c4cd789c9 AVX512: vsqrtss/sd encoding and intrinsics implementation. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12102

llvm-svn: 248116
 2015-09-20 09:13:41 +00:00
Asaf Badouh 572bbceecc [X86][AVX512DQ] Add fpclass instruction 
Differential Revision: http://reviews.llvm.org/D12931

llvm-svn: 248115
 2015-09-20 08:46:07 +00:00
Igor Breger 1d55f20bee AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, vshufi32x4 
Added tests for intrinsics.

Differential Revision: http://reviews.llvm.org/D12525

llvm-svn: 248113
 2015-09-20 07:18:53 +00:00
Igor Breger 0ede3cbb5c AVX512: Implement instructions encoding, lowering and intrinsics 
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.

Differential Revision: http://reviews.llvm.org/D11893

llvm-svn: 248111
 2015-09-20 06:52:42 +00:00
Igor Breger 0dcd8bcf24 AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, vpconflictq, vpconflictd 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11931

llvm-svn: 246750
 2015-09-03 09:05:31 +00:00
Asaf Badouh d2c3599c5f [X86][AVX512VLBW] add support in byte shift and SAD 
add byte shift left/right
add SAD - compute sum of absolute differences

Differential Revision: http://reviews.llvm.org/D12479

llvm-svn: 246654
 2015-09-02 14:21:54 +00:00
Igor Breger 1e58e8adf6 AVX512: Implemented encoding and intrinsics for VGETMANTPD/S , VGETMANTSD/S instructions 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11593

llvm-svn: 246642
 2015-09-02 11:18:55 +00:00
Igor Breger a6297c701e AVX512: Implemented encoding and intrinsics for vshufps/d. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11709

llvm-svn: 246640
 2015-09-02 10:50:58 +00:00
Igor Breger f6f1bb6ddc AVX512: Implemented intrinsics for valign. 
Differential Revision: http://reviews.llvm.org/D12526

llvm-svn: 246551
 2015-09-01 15:27:18 +00:00
Igor Breger f3ded811b2 AVX512: Implemented encoding and intrinsics for vdbpsadbw 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12491

llvm-svn: 246436
 2015-08-31 13:09:30 +00:00
Igor Breger 2ae0fe3ac3 AVX512: Implemented encoding and intrinsics for vpalignr 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12270

llvm-svn: 246428
 2015-08-31 11:14:02 +00:00
Igor Breger 8352a0ddf2 AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructions 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11528

llvm-svn: 243390
 2015-07-28 06:53:28 +00:00
Igor Breger f2460112ad Implemented encoding and intrinsics of the following instructions 
vunpckhps/pd, vunpcklps/pd, 
  vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11509

llvm-svn: 243246
 2015-07-26 14:41:44 +00:00
Igor Breger 074a64e72c AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation 
Added tests for DAG lowering ,encoding and intrinsic

Differential Revision: http://reviews.llvm.org/D11218

llvm-svn: 243122
 2015-07-24 17:24:15 +00:00
Chandler Carruth fe414353db Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..." 
This commit broke the build. Numerous build bots broken, and it was
blocking my progress so reverting.

It should be trivial to reproduce -- enable the BPF backend and it
should fail when running llvm-tblgen.

llvm-svn: 242992
 2015-07-23 08:03:44 +00:00
Igor Breger da1b2ea955 AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation 
Added tests for DAG lowering ,encoding and intrinsic

Differential Revision: http://reviews.llvm.org/D11218

llvm-svn: 242990
 2015-07-23 07:39:21 +00:00
Asaf Badouh a5b2e5e2a7 [X86][AVX512] add reduce/range/scalef/rndScale 
include encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D11222

llvm-svn: 242896
 2015-07-22 12:00:43 +00:00
Elena Demikhovsky a26f10ce18 AVX-512: Added intrinsics for VCVT* instructions. 
All SKX forms. All VCVT instructions for float/double/int/long types.

Differential Revision: http://reviews.llvm.org/D11343

llvm-svn: 242877
 2015-07-22 08:56:00 +00:00
Igor Breger f7fd547e27 AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11351

llvm-svn: 242761
 2015-07-21 07:11:28 +00:00
Simon Pilgrim d85cae3d52 [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructions 
This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it.

As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions.

From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level.

Differential Revision: http://reviews.llvm.org/D10146

llvm-svn: 241508
 2015-07-06 20:46:41 +00:00
Simon Pilgrim 8b756596fc [X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN opcodes and remove the X86 implementation 
With the completion of D9746 there is now a common implementation of integer signed/unsigned min/max nodes, removing the need for the equivalent X86 specific implementations.

This patch removes the old X86ISD nodes, legalizes the relevant SSE2/SSE41/AVX2/AVX512 instructions for the ISD versions and converts the small amount of existing X86 code.

Differential Revision: http://reviews.llvm.org/D10947

llvm-svn: 241506
 2015-07-06 20:30:47 +00:00
Asaf Badouh c6f3c82ffc [X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale 
pmulhrsw

review:
http://reviews.llvm.org/D10948

llvm-svn: 241443
 2015-07-06 14:03:40 +00:00
Asaf Badouh 73f26f8ffc [x86][AVX512] add Multiply High Op 
include encoding and intrinsics tests.

review
http://reviews.llvm.org/D10896

llvm-svn: 241406
 2015-07-05 12:23:20 +00:00
Elena Demikhovsky 30bc4ca313 AVX-512: all forms of SCATTER instruction on SKX, 
encoding, intrinsics and tests.

llvm-svn: 240936
 2015-06-29 12:14:24 +00:00
Igor Breger a7a8e9a018 AVX-512: Implemented missing encoding and intrinsics for FMA instructions 
Added tests for DAG lowering ,encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D10796

llvm-svn: 240926
 2015-06-29 09:10:00 +00:00
NAKAMURA Takumi 7bffb6954d Whitespace. 
llvm-svn: 240924
 2015-06-29 04:50:09 +00:00
Asaf Badouh 7ec4b7a8bb [x86][AVX512] 
Add vscalef support
include encoding and intrinsics


review:
http://reviews.llvm.org/D10730

llvm-svn: 240906
 2015-06-28 14:30:39 +00:00
Elena Demikhovsky 6a1a357f1f AVX-512: Added all SKX forms of GATHER instructions. 
Added intrinsics.
Added encoding and tests.

llvm-svn: 240905
 2015-06-28 10:53:29 +00:00
Elena Demikhovsky 5e2f8c4231 AVX-512: Added all forms of VPABS instruction 
Added all intrinsics, tests for encoding, tests for intrinsics.

llvm-svn: 240386
 2015-06-23 08:19:46 +00:00
Elena Demikhovsky 55a997437c AVX-512: added VPSHUFB instruction - all SKX forms 
Added intrinsics and encoding tests.

llvm-svn: 240277
 2015-06-22 13:00:42 +00:00
Elena Demikhovsky e77566112c AVX-512: Added intrinsics for VPERMT2W/D/Q/PS/PD and 
VPERMI2W/D/Q/PS/PD instructions.
Added tests.

llvm-svn: 240256
 2015-06-22 06:45:48 +00:00
Asaf Badouh 81f03c30a5 [AVX512] 
add instructions: VPAVGB and VPAVGW


review
http://reviews.llvm.org/D10504

llvm-svn: 240012
 2015-06-18 12:30:53 +00:00
Igor Breger dfcc3d31a7 AVX-512: cvtusi2ss/d intrinsics. 
Change builtin function name and signature ( add third parameter - rounding mode ).
Added tests for intrinsics.

Differential Revision: http://reviews.llvm.org/D10473

llvm-svn: 239888
 2015-06-17 07:23:57 +00:00
Asaf Badouh 02d126cb9d [AVX512] add integer min/max intrinsics support. 
review:
http://reviews.llvm.org/D10439

llvm-svn: 239806
 2015-06-16 08:39:27 +00:00
Igor Breger abe4a79b75 AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL. 
Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D10430

llvm-svn: 239694
 2015-06-14 12:44:55 +00:00
Igor Breger 00d9f8457b AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL 
Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.

Differential Revision: http://reviews.llvm.org/D10310

llvm-svn: 239300
 2015-06-08 14:03:17 +00:00
Asaf Badouh 402ebb34af re-apply 238809 
AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
CR:
http://reviews.llvm.org/D9991

llvm-svn: 238923
 2015-06-03 13:41:48 +00:00
Asaf Badouh 8d897dd05f revert 238809 
llvm-svn: 238810
 2015-06-02 07:45:19 +00:00
Asaf Badouh 17de10f37e AVX-512: Implemented GETEXP instruction for KNL and SKX 
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.

llvm-svn: 238809
 2015-06-02 07:18:14 +00:00
Elena Demikhovsky b8573cba02 AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/D 
instructions. These intrinsics are comming with rounding mode.
Added intrinsics for MAXSS/D, MINSS/D - with and without  sae.

By Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 237560
 2015-05-18 07:24:19 +00:00
Elena Demikhovsky 0d7e9364d1 AVX-512: Added SKX instructions and intrinsics: 
{add/sub/mul/div/} x {ps/pd} x {128/256} 2. max/min with sae

By Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236971
 2015-05-11 06:05:05 +00:00
Elena Demikhovsky 29792e9a80 AVX-512: Added all forms of FP compare instructions for KNL and SKX. 
Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.

By Igor Breger (igor.breger@intel.com)

llvm-svn: 236714
 2015-05-07 11:24:42 +00:00
Elena Demikhovsky 52266388f8 AVX-512: added integer "add" and "sub" instructions with saturation for SKX 
with intrinsics and tests

by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236418
 2015-05-04 12:35:55 +00:00
Elena Demikhovsky 2557a22be7 AVX-512: Added VPACK* instructions forms for KNL and SKX 
and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236414
 2015-05-04 09:14:02 +00:00
Sanjay Patel f75ee4dc07 [x86] remove RCPPS and RSQRTPS intrinsic instruction definitions 
We don't need codegen-only intrinsic instructions for the vector forms of these instructions.

This makes the reciprocal estimate instruction lowering identical to how we handle normal
square roots: (V)SQRTPS / (V)SQRTPD.

No existing regression tests fail with this patch.

Differential Revision: http://reviews.llvm.org/D9301

llvm-svn: 236013
 2015-04-28 18:48:45 +00:00
Elena Demikhovsky ae51853924 AVX-512: Added "pandn" intrinsics set 
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 235971
 2015-04-28 08:12:42 +00:00
Sanjay Patel 8fd573e87f fix 80-cols; NFC 
llvm-svn: 235902
 2015-04-27 17:45:44 +00:00
Sanjay Patel 912315811e fix typos; NFC 
llvm-svn: 235896
 2015-04-27 17:03:31 +00:00
Elena Demikhovsky 50b88ddb87 AVX-512: Added logical and arithmetic instructions for SKX 
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 235375
 2015-04-21 10:27:40 +00:00
Elena Demikhovsky 1eeece1285 AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB 
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 233906
 2015-04-02 10:51:40 +00:00
Elena Demikhovsky 98de9d6360 AVX-512: added intrinsics for VPAND, VPOR and VPXOR 
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 233525
 2015-03-30 08:30:34 +00:00
Quentin Colombet f59b2d034c [X86] Fix a regression introduced by r223641. 
The permps and permd instructions have their operands swapped compared to the
intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP
category.

I did not create a new category for those two, as they are the only one AFAICT
in that case.

<rdar://problem/20108262>

llvm-svn: 232085
 2015-03-12 19:34:12 +00:00
Elena Demikhovsky 52e81bc499 AVX-512: recommitted 229837 + bugfix + test 
llvm-svn: 230223
 2015-02-23 15:12:31 +00:00
Eric Christopher 0d94fa98e5 Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics." 
The instructions were being generated on architectures that don't support avx512.

This reverts commit r229837.

llvm-svn: 229942
 2015-02-20 00:45:28 +00:00
Elena Demikhovsky 69e8b45b13 AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics. 
llvm-svn: 229837
 2015-02-19 10:48:04 +00:00
Elena Demikhovsky 714f23bcdb AVX-512: Added support for FP instructions with embedded rounding mode. 
By Asaf Badouh <asaf.badouh@intel.com>

llvm-svn: 229645
 2015-02-18 07:59:20 +00:00
Elena Demikhovsky 7b0dd39db6 AVX-512: Added FMA intrinsics with rounding mode 
By Asaf Badouh and Elena Demikhovsky

Added special nodes for rounding: FMADD_RND, FMSUB_RND..
It will prevent merge between nodes with rounding and other standard nodes.

llvm-svn: 227303
 2015-01-28 10:21:27 +00:00
Elena Demikhovsky fcea06acb5 AVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targets 
by Asaf Badouh

http://reviews.llvm.org/D6456

llvm-svn: 224764
 2014-12-23 10:30:39 +00:00
Elena Demikhovsky 949b0d46bf AVX-512: Added all forms of BLENDM instructions, 
intrinsics, encoding tests for AVX-512F and skx instructions.

llvm-svn: 224707
 2014-12-22 13:52:48 +00:00
Elena Demikhovsky 72860c341e AVX-512: Added EXPAND instructions and intrinsics. 
llvm-svn: 224241
 2014-12-15 10:03:52 +00:00
Cameron McInally 5fb084e798 [AVX512] Add support for 512b variable bit shift intrinsics. 
llvm-svn: 224028
 2014-12-11 17:13:05 +00:00
Elena Demikhovsky 908dbf48c8 AVX-512: Added all forms of COMPRESS instruction 
+ intrinsics + tests

llvm-svn: 224019
 2014-12-11 15:02:24 +00:00
Elena Demikhovsky 68e04b8613 X86 intrinsics moved form X86ISelLowering.cpp to X86IntrinsicsInfo.h 
X86ISelLowering.cpp has a long switch for intrinsics. I moved a part of
this long switch to the new intrinsics table in X86IntrinsicsInfo.h.
No functional changes, just code and compile time optimization.

llvm-svn: 223641
 2014-12-08 09:03:08 +00:00
Ahmed Bougacha 8b54286d1c [X86] Refactor PMOV[SZ]Xrm to add missing AVX2 patterns. 
Most patterns will go away once the extload legalization changes land.

Differential Revision: http://reviews.llvm.org/D6125

llvm-svn: 223567
 2014-12-06 01:31:07 +00:00
Michael Liao 5bf9578ce4 [X86] Clean up whitespace as well as minor coding style 
llvm-svn: 223339
 2014-12-04 05:20:33 +00:00
Elena Demikhovsky 905a5a606f AVX-512: Scalar ERI intrinsics 
including SAE mode and memory operand.
Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future.

The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect.
I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction.

http://reviews.llvm.org/D6378

llvm-svn: 222820
 2014-11-26 10:46:49 +00:00
Cameron McInally 9b7c15a364 [AVX512] Add 512b integer shift by variable intrinsics and patterns. 
llvm-svn: 222786
 2014-11-25 20:41:51 +00:00
Cameron McInally 73a6bca32b [AVX512] Add integer shift by immediate intrinsics. 
llvm-svn: 221811
 2014-11-12 19:58:54 +00:00
Elena Demikhovsky be8808dc3f AVX-512: Intrinsics for ERI 
3 instructions: vrcp28, vrsqrt28, vexp2, only vector forms.
Intrinsics include SAE (Suppres All Exceptions) parameter.

http://reviews.llvm.org/D6214

llvm-svn: 221774
 2014-11-12 07:31:03 +00:00
Robert Khasanov b51bb22611 [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VPCMP/VPCMPU{BWDQ} 
Added CMP_MASK_CC intrinsic type.
Added tests for intrinsics.

Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>

llvm-svn: 219316
 2014-10-08 15:49:26 +00:00
Robert Khasanov 28a7df0b5f [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VCMPGT{BWDQ}. 
Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>

llvm-svn: 218670
 2014-09-30 12:15:52 +00:00
Robert Khasanov 5aa4445bde [AVX512] Added intrinsics for 128- and 256-bit versions of VCMPEQ{BWDQ} 
Fixed lowering of this intrinsics in case when mask is v2i1 and v4i1.
Now cmp intrinsics lower in the following way:
 (i8 (int_x86_avx512_mask_pcmpeq_q_128
             (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
 (i8 (bitcast
   (v8i1 (insert_subvector undef,
           (v2i1 (and (PCMPEQM %a, %b),
                      (extract_subvector
                         (v8i1 (bitcast %mask)), 0))), 0))))

llvm-svn: 218669
 2014-09-30 11:41:54 +00:00
Robert Khasanov b25e562d14 [AVX512] Added intrinsics for VPCMPEQB and VPCMPEQW. 
Added new operand type for intrinsics (IIT_V64)

llvm-svn: 218668
 2014-09-30 11:32:22 +00:00
Robert Khasanov a27c8e0fd9 [AVX512] Enabled intrinsics for VPCMPEQD and VPCMPEQQ. 
Added CMP_MASK intrinsic type

llvm-svn: 218667
 2014-09-30 11:19:50 +00:00
Elena Demikhovsky 0f54a0b02a Fixed compilation problem on Windows (initialization of non-aggregate type). 
After commit 217131.

llvm-svn: 217134
 2014-09-04 07:20:39 +00:00
Elena Demikhovsky 228ab3d7b3 X86 Intrinsics table - changed to a static table sorted by intrinsic id. 
Used binary search over the tables.

llvm-svn: 217131
 2014-09-04 06:34:34 +00:00
Elena Demikhovsky 22e735d725 X86 intrinsics table - simplifies intrinsics lowering. 
The tables are initialized when X86TargetLowering object is created.

llvm-svn: 216345
 2014-08-24 09:19:56 +00:00
Elena Demikhovsky c0b420fdf5 Reverted last commit 
llvm-svn: 215827
 2014-08-17 09:36:07 +00:00
Elena Demikhovsky 2bb991a0c5 Added a table for intrinsics on X86. 
It should remove dosens of lines in handling instrinsics (in a huge switch) and give an easy way to add new intrinsics.
I did not completed to move al intrnsics to the table, I'll do this in the upcomming commits.

llvm-svn: 215826
 2014-08-17 09:00:20 +00:00