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443 Commits

Author SHA1 Message Date
Kevin Enderby 6fd9624843 Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target 
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. 

llvm-svn: 166982
 2012-10-29 23:27:20 +00:00
Kevin Enderby b23926d395 Fix a bug where a 32-bit address with the high bit does not get symbolicated 
because the value is incorrectly being signed extended when passed to
SymbolLookUp().

llvm-svn: 166234
 2012-10-18 21:49:18 +00:00
Tim Northover 0c97e76492 Fix the handling of edge cases in ARM shifted operands. 
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

llvm-svn: 164455
 2012-09-22 11:18:12 +00:00
Tim Northover 00e071ad52 Diagnose invalid alignments on duplicating VLDn instructions. 
Patch by Chris Lidbury.

llvm-svn: 163323
 2012-09-06 15:27:12 +00:00
Tim Northover fb3cdd83b0 Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions. 
Patch by Chris Lidbury.

llvm-svn: 163321
 2012-09-06 15:17:49 +00:00
Richard Smith 228e6d4cf3 Fix integer undefined behavior due to signed left shift overflow in LLVM. 
Reviewed offline by chandlerc.

llvm-svn: 162623
 2012-08-24 23:29:28 +00:00
Craig Topper f6add7e667 Remove unnecessary include of ARMGenInstrInfo.inc. 
llvm-svn: 162086
 2012-08-17 06:21:09 +00:00
Jim Grosbach ecaef49f59 Switch the fixed-length disassembler to be table-driven. 
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
  Previous: 35.5s
  New:       8.9s

TEXT size:
  Previous: 447,251
  New:      297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

llvm-svn: 161888
 2012-08-14 19:06:05 +00:00
Jiangning Liu 6a43bf7d74 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. 
llvm-svn: 161162
 2012-08-02 08:29:50 +00:00
Jiangning Liu 288e1af8c8 Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. 
llvm-svn: 161161
 2012-08-02 08:21:27 +00:00
Sylvestre Ledru 35521e2310 Fix a typo (the the => the) 
llvm-svn: 160621
 2012-07-23 08:51:15 +00:00
Richard Barton 1dc44dcedd Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! 
llvm-svn: 159989
 2012-07-10 12:51:09 +00:00
Chad Rosier aeed158f75 Revert r159938 (and r159945) to appease the buildbots. 
llvm-svn: 159960
 2012-07-09 20:43:34 +00:00
Richard Barton 5beef2d242 Oops - correct broken disassembly for VMOV 
llvm-svn: 159945
 2012-07-09 18:20:02 +00:00
Richard Barton c9e1c94fae Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) 
llvm-svn: 159938
 2012-07-09 16:41:33 +00:00
Richard Barton f1ef87ddbb Correct decoder for T1 conditional B encoding 
llvm-svn: 158055
 2012-06-06 09:12:53 +00:00
NAKAMURA Takumi 70c1aa0bb5 ARMDisassembler.cpp: Fix utf8 char in comments. 
llvm-svn: 157292
 2012-05-22 21:47:02 +00:00
Kevin Enderby cabbae653e Tweak to the fix in r156212, as with the change in removing the shift the 
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .

llvm-svn: 156213
 2012-05-04 22:09:52 +00:00
Kevin Enderby 8ce1ada1be Fix a bug in the ARM disassembler for wide branch conditional instructions 
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046

llvm-svn: 156212
 2012-05-04 22:02:27 +00:00
Kevin Enderby 914223010c Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits 
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!

llvm-svn: 156118
 2012-05-03 22:41:56 +00:00
Silviu Baranga 9560af848c Fixed disassembler for vstm/vldm ARM VFP instructions. 
llvm-svn: 156077
 2012-05-03 16:38:40 +00:00
Jim Grosbach 9d8f6f3d9d ARM: Tweak tADDrSP definition for consistent operand order. 
Make the operand order of the instruction match that of the asm syntax.

llvm-svn: 155747
 2012-04-27 23:51:33 +00:00
Richard Barton f435b09eaf Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. 
llvm-svn: 155700
 2012-04-27 08:42:59 +00:00
Richard Barton e9600009e9 Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector 
llvm-svn: 155439
 2012-04-24 11:13:20 +00:00
Silviu Baranga ca45af9a75 Added support for disassembling unpredictable swp/swpb ARM instructions. 
llvm-svn: 155004
 2012-04-18 14:18:57 +00:00
Silviu Baranga 41f1fcd80e Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. 
llvm-svn: 155001
 2012-04-18 13:12:50 +00:00
Kevin Enderby 29ae538647 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .

llvm-svn: 154884
 2012-04-17 00:49:27 +00:00
Kevin Enderby 40d4e47003 Fix a few more places in the ARM disassembler so that branches get 
symbolic operands added when using the C disassembler API.

llvm-svn: 154628
 2012-04-12 23:13:34 +00:00
Kevin Enderby 72f18bbcff Fixed a case of ARM disassembly getting an assert on a bad encoding 
of a VST instruction.

llvm-svn: 154544
 2012-04-11 22:40:17 +00:00
Kevin Enderby d2980cd041 Fix ARM disassembly of VLD instructions with writebacks.  And add test a case 
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .

llvm-svn: 154459
 2012-04-11 00:25:40 +00:00
Dylan Noblesmith 7a3973d3e0 ARMDisassembler: drop bogus dependency on ARMCodeGen 
And indirectly, a dependency on most of the core LLVM optimization
libraries.

llvm-svn: 153957
 2012-04-03 15:48:14 +00:00
Craig Topper f6e7e12f75 Remove unnecessary llvm:: qualifications 
llvm-svn: 153500
 2012-03-27 07:21:54 +00:00
Silviu Baranga 4afd7d2316 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 
llvm-svn: 153252
 2012-03-22 14:14:49 +00:00
Silviu Baranga d213f2111a Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 
llvm-svn: 153251
 2012-03-22 13:24:43 +00:00
Kevin Enderby 7e7d5eefb2 Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test 
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .

llvm-svn: 153218
 2012-03-21 20:54:32 +00:00
Silviu Baranga 32a49333ec The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
llvm-svn: 153089
 2012-03-20 15:54:56 +00:00
Craig Topper ca658c2264 Use uint16_t to store registers and opcode in static tables in the target specific backends. 
llvm-svn: 152537
 2012-03-11 07:16:55 +00:00
Jim Grosbach eed9992b26 Tidy up. Remove dead code that slipped into previous commit. 
llvm-svn: 152184
 2012-03-07 00:52:39 +00:00
Jim Grosbach ed428bc1ce ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

llvm-svn: 152157
 2012-03-06 23:10:38 +00:00
Jim Grosbach 13a292cc74 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150
 2012-03-06 22:01:44 +00:00
Kevin Enderby 520eb3ba8a Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. 
llvm-svn: 152127
 2012-03-06 18:33:12 +00:00
Jim Grosbach e5307f9019 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

llvm-svn: 152063
 2012-03-05 21:43:40 +00:00
Jim Grosbach c988e0c521 ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045
 2012-03-05 19:33:30 +00:00
Derek Schuff 56b662ce0f Make MemoryObject accessor members const again 
llvm-svn: 151687
 2012-02-29 01:09:06 +00:00
Kevin Enderby 1489b523c3 Fix the symbolic operand added for the C disassmbler API for the ARM bl 
thumb instruction.  The PC adjustment is +4 in Thumb mode and +8 in ARM mode.

llvm-svn: 151530
 2012-02-27 18:15:15 +00:00
Kevin Enderby 6fbcd8d439 Updated the llvm-mc disassembler C API to support for the X86 target. 
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166

llvm-svn: 151267
 2012-02-23 18:18:17 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Benjamin Kramer 428704eb52 Make the EDis tables const. 
llvm-svn: 150304
 2012-02-11 14:51:07 +00:00
Craig Topper e55c556a24 Convert assert(0) to llvm_unreachable 
llvm-svn: 149961
 2012-02-07 02:50:20 +00:00
Derek Schuff 8b2dcad4b5 Enable streaming of bitcode 
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.

llvm-svn: 149918
 2012-02-06 22:30:29 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Jim Grosbach 4a5c887370 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Jim Grosbach 88ac761aa4 ARM NEON refactor VST2 w/ writeback instructions. 
In addition to improving the representation, this adds support for assembly
parsing of these instructions.

llvm-svn: 146588
 2011-12-14 21:32:11 +00:00
Jim Grosbach 8d24618975 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
 2011-12-14 19:35:22 +00:00
Daniel Dunbar 27a7489a03 LLVMBuild: Remove trailing newline, which irked me. 
llvm-svn: 146409
 2011-12-12 19:48:00 +00:00
Jim Grosbach d146a02c79 ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
 2011-12-09 21:28:25 +00:00
Matt Beaumont-Gay 23c30b90e3 Remove unused variable 
llvm-svn: 145517
 2011-11-30 19:53:11 +00:00
Jim Grosbach a68c9a847e ARM parsing for VLD1 all lanes, with writeback. 
llvm-svn: 145510
 2011-11-30 19:35:44 +00:00
Jim Grosbach 5ee209ce3a ARM assembly parsing and encoding for four-register VST1. 
llvm-svn: 145450
 2011-11-29 22:58:48 +00:00
Jim Grosbach 98d032fd67 ARM assembly parsing and encoding for three-register VST1. 
llvm-svn: 145442
 2011-11-29 22:38:04 +00:00
Daniel Dunbar 539d0a8a09 build/CMake: Finish removal of add_llvm_library_dependencies. 
llvm-svn: 145420
 2011-11-29 19:25:30 +00:00
Owen Anderson 05060f0748 Fix a misplaced paren bug. 
llvm-svn: 144692
 2011-11-15 20:30:41 +00:00
Owen Anderson 0ac9058f89 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
llvm-svn: 144683
 2011-11-15 19:55:00 +00:00
Daniel Dunbar 52823cc91c build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

llvm-svn: 144444
 2011-11-12 02:10:57 +00:00
Jim Grosbach 8ca13deecf Re-apply 144430, this time with the associated isel and disassmbler bits. 
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

llvm-svn: 144437
 2011-11-12 00:31:53 +00:00
Benjamin Kramer 48b5bbffed Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. 
llvm-svn: 144384
 2011-11-11 12:39:41 +00:00
Daniel Dunbar bf9bba47a1 build: Add initial cut at LLVMBuild.txt files. 
llvm-svn: 143634
 2011-11-03 18:53:17 +00:00
Owen Anderson ec5c5f7008 The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. 
llvm-svn: 143553
 2011-11-02 17:46:18 +00:00
Owen Anderson fad59dab62 Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. 
llvm-svn: 143552
 2011-11-02 17:41:23 +00:00
Owen Anderson 69e54a740c Fix disassembly of some VST1 instructions. 
llvm-svn: 143507
 2011-11-01 22:18:13 +00:00
Jim Grosbach 05df460269 ARM VST1 w/ writeback assembly parsing and encoding. 
llvm-svn: 143369
 2011-10-31 21:50:31 +00:00
Owen Anderson 40703f4252 More not-crashing NEON disassembly updates for the vld refactoring. 
llvm-svn: 143351
 2011-10-31 17:17:32 +00:00
Owen Anderson dde461c8b1 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
llvm-svn: 143208
 2011-10-28 18:02:13 +00:00
Owen Anderson 8a6ebd085a Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. 
llvm-svn: 143162
 2011-10-27 22:53:10 +00:00
Jim Grosbach 17ec1a19e5 ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.

llvm-svn: 142882
 2011-10-25 00:14:01 +00:00
Jim Grosbach 92fd05ecdc ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.

llvm-svn: 142876
 2011-10-24 23:26:05 +00:00
Jim Grosbach 2098cb1e6f ARM refactor am6offset usage for VLD1. 
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.

llvm-svn: 142853
 2011-10-24 21:45:13 +00:00
Owen Anderson 295b1e84ce Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. 
llvm-svn: 142817
 2011-10-24 18:04:29 +00:00
Benjamin Kramer 0d6d098841 Move various generated tables into read-only memory, fixing up const correctness along the way. 
llvm-svn: 142726
 2011-10-22 16:50:00 +00:00
Jim Grosbach 11c0b347c6 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach 118b38cbf1 Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach 846bcff7c7 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach c4360fe575 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach 2f2e3c4737 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Jim Grosbach 79ebc51c45 Tidy up. Trailing whitespace. 
llvm-svn: 142591
 2011-10-20 17:28:20 +00:00
Chad Rosier 34957911e7 Removed set, but unused variables. 
Patch by Joe Abbey <jabbey@arxan.com>.

llvm-svn: 142223
 2011-10-17 18:48:30 +00:00
Richard Trieu 8b478360ef Fix a non-firing assert. Change: 
assert("bad SymbolicOp.VariantKind");
To:
    assert(0 && "bad SymbolicOp.VariantKind");

llvm-svn: 142000
 2011-10-14 20:50:26 +00:00
Eli Friedman a7ad9f3932 Fix undefined shift. Patch by Ahmed Charles. 
llvm-svn: 141914
 2011-10-13 23:36:06 +00:00
Owen Anderson 44f76eafae SETEND is not allowed in an IT block. 
llvm-svn: 141874
 2011-10-13 17:58:39 +00:00
Jim Grosbach a098a891ab ARM addrmode5 represents the 'U' bit of the encoding backwards. 
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

llvm-svn: 141819
 2011-10-12 21:59:02 +00:00
Jim Grosbach 54a20ed0f1 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Jim Grosbach 8007320902 addrmode2 is gone from these, so no need for the reg0 operand. 
llvm-svn: 141794
 2011-10-12 18:11:24 +00:00
Owen Anderson 6a5c150e9c Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. 
llvm-svn: 141339
 2011-10-06 23:33:11 +00:00
Kevin Enderby 5dcda64338 Adding back support for printing operands symbolically to ARM's new disassembler 
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129
 2011-10-04 22:44:48 +00:00
Jim Grosbach efc761a1eb ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Owen Anderson f01e2de5e6 ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
llvm-svn: 140560
 2011-09-26 21:06:22 +00:00
Owen Anderson 987a878946 Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
llvm-svn: 140415
 2011-09-23 21:07:25 +00:00
Owen Anderson ffa8428acf Revert r140412. This affects more instructions than intended. 
llvm-svn: 140413
 2011-09-23 21:02:01 +00:00
Owen Anderson 7591d0c363 Thumb2 register-shifted-register loads cannot target the PC or the SP. 
llvm-svn: 140412
 2011-09-23 21:00:32 +00:00
Owen Anderson 163be01d69 tMOVSr is not allowed in an IT block either. 
llvm-svn: 140104
 2011-09-19 23:57:20 +00:00