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5 Commits

Author SHA1 Message Date
Matt Arsenault e66621b306 AMDGPU: Add s_dcache_* instructions 
llvm-svn: 248533
 2015-09-24 19:52:27 +00:00
Matt Arsenault d6adfb401c AMDGPU: Add cache invalidation instructions. 
These are necessary for implementing mem_fence for
OpenCL 2.0.

The VI assembler tests are disabled since it seems to be
using the wrong encoding or opcode.

llvm-svn: 248532
 2015-09-24 19:52:21 +00:00
Matt Arsenault e8df879948 AMDGPU: Improve accuracy of instruction rates for some FP instructions 
llvm-svn: 245774
 2015-08-22 00:50:41 +00:00
Matt Arsenault 6adf07a92e AMDGPU: Move CI instructions into CIInstructions.td 
There are still a couple of CI patterns left in SIInstructions.

llvm-svn: 245767
 2015-08-22 00:16:34 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00