e22f9181f7
Support for read / write from explicit registers with FlagVT type.
...
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
6a31777c8e
Skip over srcvalue nodes when generating ISEL code.
...
llvm-svn: 24704
2005-12-14 02:21:57 +00:00
6148153230
Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ...
...
llvm-svn: 24680
2005-12-12 23:45:21 +00:00
7e4c01eee3
At top of generated isel SelectCode() is this:
...
if (!N.Val->hasOneUse()) {
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
if (CGMI != CodeGenMap.end()) return CGMI->second;
}
Suppose a DAG like this:
X
^ ^
/ \
USE1 USE2
Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!
The fix is to always query CodeGenMap.
llvm-svn: 24679
2005-12-12 23:22:48 +00:00
cdb16ef6f3
Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible.
...
llvm-svn: 24669
2005-12-12 19:37:43 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
0da396ffe2
Stop emitting a redudant type check for complex pattern node.
...
llvm-svn: 24655
2005-12-10 01:57:33 +00:00
bac252c289
For instructions which produce no result, e.g. store, chain's Resno == 0.
...
llvm-svn: 24652
2005-12-10 00:09:17 +00:00
433573f4c6
Add a new SDTCisPtrTy constraint, which indicates that an operand must have
...
the same type as the pointer type for a target.
llvm-svn: 24649
2005-12-09 22:57:42 +00:00
499ab2a9fa
* Do not allow nodes which produce chain results (e.g. loads) to be folded if
...
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
llvm-svn: 24647
2005-12-09 22:45:35 +00:00
c1f911a238
Prevent folding of instructions which produce chains that have more than 1 real use
...
llvm-svn: 24643
2005-12-09 06:06:08 +00:00
f423a17e33
* Make sure complex pattern operands are selected first since their select
...
functions can return false and causing the instruction pattern match to fail.
* Code clean up.
llvm-svn: 24642
2005-12-09 00:48:42 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
...
* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
...
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
0fe76d1585
* Infer instruction property hasCtrlDep from pattern if it has one.
...
* Fixed a bug related to hasCtrlDep property use.
llvm-svn: 24610
2005-12-05 23:08:55 +00:00
ba369ae8f1
Implement PR673: for explicit register references, use type information
...
if available
llvm-svn: 24597
2005-12-05 02:36:37 +00:00
3717b4c830
Add some methods
...
llvm-svn: 24596
2005-12-05 02:35:08 +00:00
d49489f01e
Generate code to silence bogus GCC warnings.
...
llvm-svn: 24593
2005-12-05 00:48:51 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
...
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
fed83adbe3
Teach tblgen to accept register source operands in patterns, e.g.
...
def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.
llvm-svn: 24557
2005-12-01 00:18:45 +00:00
faad542d24
Nuke CodeGenInstruction's ValueType member, it is no longer used.
...
llvm-svn: 24556
2005-12-01 00:12:04 +00:00
cdf2c67888
Stop checking the ValueType of the CodeGenInstruction. Instead, use the
...
ValueType from the RegisterClass or Operands. This step is necessary to
allow RegisterClasses to have multiple ValueTypes.
llvm-svn: 24555
2005-12-01 00:06:14 +00:00
e479ccb27b
fit into 80 columns
...
llvm-svn: 24554
2005-11-30 23:58:18 +00:00
3e63dc00da
Make the code generated by tblgen return the result of SelectNodeTo, to
...
permit future changes.
llvm-svn: 24553
2005-11-30 23:08:45 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
...
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
f621b333f3
Fix some copy and paste typos.
...
llvm-svn: 24540
2005-11-30 18:37:14 +00:00
c8af0cb893
Better error message when unrecognized opcode is seen.
...
llvm-svn: 24519
2005-11-29 18:44:58 +00:00
4d0251ad55
Add the new vector types to tablegen
...
llvm-svn: 24514
2005-11-29 06:19:38 +00:00
f2807be3da
Initialize this variable on all paths, fixing a crasher in windows. Thanks
...
to JeffC for pointing this out.
llvm-svn: 24426
2005-11-19 07:48:33 +00:00
6bc0304c91
Teach tblgen about instruction operands that have multiple MachineInstr
...
operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
llvm-svn: 24424
2005-11-19 07:05:57 +00:00
a70c7dff2e
Validate that the input to 'Pat' patterns is sane.
...
llvm-svn: 24393
2005-11-17 17:43:52 +00:00
2a230e1c1a
teach tblgen to be smart enough to handle tglobaladdr nodes
...
llvm-svn: 24391
2005-11-17 07:39:45 +00:00
b22950df6c
fix a tblgen bug that Evan ran into, where we would lose the '$src' name
...
on patterns like "(set R32:$dst, (i32 imm:$src))"
llvm-svn: 24383
2005-11-16 23:14:54 +00:00
d6d3afb05e
1. Remove ranges from itinerary data.
...
2. Tidy up the subtarget emittined code.
llvm-svn: 24172
2005-11-03 22:47:41 +00:00
64209fd14b
Reject integer literals that are out of range for their type.
...
llvm-svn: 24162
2005-11-03 05:46:11 +00:00
590176be16
Add support for immediates directly in the pattern, this allows itanium to
...
define:
def : Pat<(i1 1), (CMPEQ r0, r0)>;
llvm-svn: 24149
2005-11-02 06:49:14 +00:00
802748cd61
Allow itineraries to be passed through the Target Machine.
...
llvm-svn: 24139
2005-11-01 20:06:59 +00:00
9e1784d738
Keep VC++ happy.
...
llvm-svn: 24137
2005-11-01 18:04:06 +00:00
0433df136f
Emit itinerary class in instruction info.
...
llvm-svn: 24122
2005-10-31 17:16:46 +00:00
3763a50d82
Generate cpu to itinerary map.
...
llvm-svn: 24121
2005-10-31 17:16:01 +00:00
d91df9d941
Make negative immediates in patterns work correctly, silence some warnings
...
building the itanium backend.
llvm-svn: 24095
2005-10-29 16:39:40 +00:00
742606ad30
Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)
...
llvm-svn: 24074
2005-10-28 22:59:53 +00:00
7ad0bed89f
Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately
...
reflect what it is.
Convert some more code over to use it.
llvm-svn: 24072
2005-10-28 22:49:02 +00:00
802bd8d94f
Use the new interface Jim added
...
llvm-svn: 24071
2005-10-28 22:43:25 +00:00
dffe5978a3
Removed Mr. Smith from the code.
...
llvm-svn: 24070
2005-10-28 21:47:29 +00:00
b04feb633f
Added method to return a vector of records for a ListInit of Def field. This
...
simplifies using list of records.
llvm-svn: 24069
2005-10-28 21:46:31 +00:00
1959575208
Add some commentary.
...
llvm-svn: 24055
2005-10-28 15:20:43 +00:00
b0aa47b043
Keep Visual Studio happy.
...
llvm-svn: 24052
2005-10-28 01:43:09 +00:00
86f002cc32
Now generating instruction itineraries for scheduling. Not my best work, but...
...
llvm-svn: 24050
2005-10-27 19:47:21 +00:00
777a26efc3
Simplify.
...
llvm-svn: 24015
2005-10-26 17:49:21 +00:00
a2b5235fac
Give full control of subtarget features over to table generated code.
...
llvm-svn: 24013
2005-10-26 17:30:34 +00:00
f277ac7caa
Condcodes are in the ISD namespace
...
llvm-svn: 24010
2005-10-26 17:02:02 +00:00
611b0c634c
Add support for CondCode's
...
llvm-svn: 24008
2005-10-26 16:59:37 +00:00
d980c46f52
Emit some boilerplate for targets
...
llvm-svn: 23983
2005-10-25 20:35:14 +00:00
1b7369b1ae
Refactored to make room for more stuff (scheduling info.)
...
llvm-svn: 23975
2005-10-25 15:16:36 +00:00
fc9f5773d0
Fix an incompatibility with GCC 4.1, thanks to Vladimir Merzliakov
...
for pointing this out!
llvm-svn: 23963
2005-10-24 15:04:15 +00:00
4f48e67c6c
Add the needed #include, emit enums with the sizes of tables, remove
...
definitions from the LLVM namespace, since they are all static.
llvm-svn: 23907
2005-10-23 22:33:08 +00:00
49f7b69997
Remove the obsolete instr selector emitter
...
llvm-svn: 23894
2005-10-23 05:47:52 +00:00
a1beea6c7d
Sort the features and processor lists for the sake of search (and maintainers.)
...
llvm-svn: 23879
2005-10-22 07:59:56 +00:00
9ed9032e22
Plugin new subtarget backend into the build.
...
llvm-svn: 23870
2005-10-21 19:05:19 +00:00
cfda85ad91
New TableGen backends for subtarget information. Only command line stuff
...
active now. Scheduling itinerary next.
llvm-svn: 23869
2005-10-21 19:00:04 +00:00
8bda5afd91
Make tblgen emit:
...
tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern!
for a bad pattern, instead of an ugly assertion.
llvm-svn: 23854
2005-10-21 01:19:59 +00:00
c9ad735e78
add support for literal immediates in patterns to match, allowing us to
...
write things like this:
def : Pat<(add GPRC:$in, 12),
(ADD12 GPRC:$in)>;
Andrew: if this isn't enough or doesn't work for you, please lemme know.
llvm-svn: 23819
2005-10-19 04:41:05 +00:00
7f6f565846
Add basic support for integer constants in pattern results.
...
llvm-svn: 23817
2005-10-19 04:30:56 +00:00
2ae2f99326
Fix some checking that was causing duraid to get a perplexing assertion
...
instead of a happy error message
llvm-svn: 23816
2005-10-19 04:12:14 +00:00
b8014e10ae
Add support for patterns that have physical registers in them. Testcase:
...
def : Pat<(trunc G8RC:$in),
(OR8To4 G8RC:$in, X0)>;
Even though this doesn't make any sense on PPC :)
llvm-svn: 23815
2005-10-19 02:07:26 +00:00
c8f899f98d
Asserting here is to violent
...
llvm-svn: 23814
2005-10-19 01:55:23 +00:00
8baf5043a8
Nate wants to define 'Pat's which turn into instructions that don't have
...
patterns. Certainly a logical request.
llvm-svn: 23810
2005-10-19 01:27:22 +00:00
ed653cbe43
Duraid pointed out that it is impolite to emit PPC:: into the IA64 backend
...
llvm-svn: 23780
2005-10-18 04:41:01 +00:00
825298b060
Make the generated code significantly more memory efficient, by using
...
SelectNodeTo instead of getTargetNode when possible.
llvm-svn: 23758
2005-10-16 01:41:58 +00:00
6b22d2554a
Implement the last major missing piece in the DAG isel generator: when emitting
...
a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction. This allows FMA32
patterns to not match double expressions for example.
llvm-svn: 23748
2005-10-15 21:34:21 +00:00
c4db8f4163
Now that we have int/fp lattice values, implement the SDTCisOpSmallerThanOp
...
type constraint. This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.
llvm-svn: 23730
2005-10-14 06:25:00 +00:00
ecaf56b21a
Fairly serious rework of the typing code to add new int/fp lattice values.
...
Overall, no functionality change yet though.
llvm-svn: 23729
2005-10-14 06:12:03 +00:00
cdf483556f
simplify the code a bit
...
llvm-svn: 23728
2005-10-14 05:08:37 +00:00
4892df38f3
Add basic support for recognizing a new SDTCisOpSmallerThanOp type constraint
...
llvm-svn: 23725
2005-10-14 04:53:53 +00:00
7b0275ba8c
Implement a couple of new (important) features.
...
1. If an operation has to be int or fp and the target only supports one
int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
for patterns involving those operators, since we do not emit the code to
check for them yet. This prevents PPC from generating FP ops currently.
Also move some code around into more logical places.
llvm-svn: 23724
2005-10-14 04:11:13 +00:00
90c5b9c83c
Do not let getLegalValueTypes return a list with duplicates in it
...
llvm-svn: 23723
2005-10-14 03:54:49 +00:00
d4ff3c1324
Emit the value type for each register class.
...
llvm-svn: 23584
2005-10-02 06:23:37 +00:00
c9f4219cfc
Rename MRegisterDesc -> TargetRegisterDesc for consistency
...
llvm-svn: 23564
2005-09-30 17:49:27 +00:00
3e020bb619
remove some more initializers
...
llvm-svn: 23562
2005-09-30 17:41:05 +00:00
ddc69bbbba
trim down the target info structs now that we have a preferred spill register class for each callee save register
...
llvm-svn: 23560
2005-09-30 17:35:22 +00:00
da6fcc9f49
Compute a preferred spill register class for each callee-save register
...
llvm-svn: 23553
2005-09-30 06:44:45 +00:00
26f5fb1277
Fix a warning
...
llvm-svn: 23550
2005-09-30 06:09:50 +00:00
1916ef75cf
Regenerate
...
llvm-svn: 23549
2005-09-30 04:53:25 +00:00
b509577605
Refactor this a bit to move ParsingTemplateArgs to only apply to classes,
...
not defs.
Implement support for forward definitions of classes. This implements
TableGen/ForwardRef.td.
llvm-svn: 23548
2005-09-30 04:53:04 +00:00
20b0e3cee4
Regenerate
...
llvm-svn: 23546
2005-09-30 04:42:56 +00:00
ad61925e27
Generate a parse error instead of a checked exception if template args are
...
used on a def.
llvm-svn: 23545
2005-09-30 04:42:31 +00:00
6e60c8fe05
regenerate
...
llvm-svn: 23543
2005-09-30 04:11:27 +00:00
e04e1384fc
Refactor the grammar a bit to implement TableGen/ForwardRef.td
...
llvm-svn: 23542
2005-09-30 04:10:49 +00:00
2a6fd61dfc
allow regs to be in multiple reg classes
...
llvm-svn: 23540
2005-09-30 01:33:48 +00:00
366fe04301
Teach tablegen to reassociate operators when possible. This allows it to
...
find all of teh pattern matches for EQV from one definition
llvm-svn: 23529
2005-09-29 22:36:54 +00:00
e86824e57a
Teach tblgen to build permutations of instructions, so that the target author
...
doesn't have to specify them manually. It currently handles associativity,
e.g. knowing that (X*Y)+Z also matches X+(Y*Z) and will be extended in
the future.
It is smart enough to not introduce duplicate patterns or patterns that can
never match.
llvm-svn: 23526
2005-09-29 19:28:10 +00:00
492e70f4ec
add support for an associative marker
...
llvm-svn: 23502
2005-09-28 20:58:06 +00:00
8bb25cd68a
Emit an error if instructions or patterns are defined but can never match.
...
Currently we check that immediate values live on the RHS of commutative
operators. Defining ORI like this, for example:
def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"ori $dst, $src1, $src2",
[(set GPRC:$dst, (or immZExt16:$src2, GPRC:$src1))]>;
results in:
tblgen: In ORI: Instruction can never match: Immediate values must be on the RHS of commutative operators!
llvm-svn: 23501
2005-09-28 19:27:25 +00:00
f74c30c281
collect commutativity information
...
llvm-svn: 23499
2005-09-28 18:28:29 +00:00
3622f15491
Prefer cheaper patterns to more expensive ones. Print the costs to the generated
...
file
llvm-svn: 23492
2005-09-28 17:57:56 +00:00
75b4c5d868
Select Constant nodes to TargetConstant nodes
...
llvm-svn: 23488
2005-09-28 16:58:06 +00:00
d455c36c91
memoize the assert results
...
llvm-svn: 23457
2005-09-26 22:10:24 +00:00
c9153266c6
Emit the switch stmt cases in alphabetical order instead of pointer order,
...
which is not stable.
llvm-svn: 23456
2005-09-26 21:59:35 +00:00
d5de8544f8
implement a fixme: only select values once, even if used multiple times.
...
llvm-svn: 23454
2005-09-26 21:53:26 +00:00
23b1d28e69
Fix VC++ build errors.
...
llvm-svn: 23431
2005-09-25 19:04:43 +00:00
cc1d38160d
memoize translations
...
llvm-svn: 23419
2005-09-24 00:50:51 +00:00
0afb14cade
Teach the DAG isel generator to emit code that creates nodes.
...
Fix a few corner cases parsing things like (i32 imm:$foo)
llvm-svn: 23417
2005-09-24 00:40:24 +00:00
cd093e868e
Emit better code (no more copies for var references), and support DAG patterns
...
(e.g. things like rotates).
llvm-svn: 23416
2005-09-23 23:16:51 +00:00
8ffb99b4fe
Fix a fixme by passing around SDOperand's instead of SDNode*'s
...
llvm-svn: 23415
2005-09-23 21:53:45 +00:00
cc8a564cb1
Emit code that matches the incoming DAG pattern and checks predicates.
...
This does not check that types match yet, but PPC only has one integer type
;-).
This also doesn't have the code to build the resultant dag.
llvm-svn: 23414
2005-09-23 21:33:23 +00:00
323a47970e
emit information about the order patterns are to be matched.
...
llvm-svn: 23413
2005-09-23 20:52:47 +00:00
abb430bad2
start filling in the switch stmt
...
llvm-svn: 23412
2005-09-23 19:36:15 +00:00
7884fffb00
Fix a minor bug, add comments
...
llvm-svn: 23370
2005-09-16 00:29:46 +00:00
59e96143a2
teach the type inference code how to infer types for instructions and node
...
xforms. Run type inference on result patterns, so we always have fully typed
results (and to catch errors in .td files).
llvm-svn: 23369
2005-09-15 22:23:50 +00:00
fedd9a5e1d
put instructions into a map instead of a vector for quick lookup
...
llvm-svn: 23368
2005-09-15 21:57:35 +00:00
f38ce8f756
when parsing instructions remember information about the types taken and
...
returned.
llvm-svn: 23367
2005-09-15 21:51:12 +00:00
a0a986c9ae
Start parsing "Pattern" nodes
...
llvm-svn: 23365
2005-09-15 21:42:00 +00:00
f79ad4cb32
rename a couple of methods, add structure for pattern parsing
...
llvm-svn: 23364
2005-09-15 02:38:02 +00:00
a155256a71
Verify that xform functions only occur in logical places
...
llvm-svn: 23363
2005-09-14 23:05:13 +00:00
991c7c973a
Promote xform fns to be explicit nodes in result patterns, and clean off
...
predicates since they will have already matched at this point.
llvm-svn: 23362
2005-09-14 23:01:59 +00:00
bc7aabce12
start building the instruction dest pattern correctly. Change the xform
...
functions to preserve the Record for the xform instead of making it into a
function name.
llvm-svn: 23361
2005-09-14 22:55:26 +00:00
e389c6154e
catch unnamed inputs
...
llvm-svn: 23360
2005-09-14 22:06:36 +00:00
030f876cf2
check that there are no unexpected operands
...
llvm-svn: 23359
2005-09-14 21:59:34 +00:00
3ced3f8b82
force all instruction operands to be named.
...
llvm-svn: 23358
2005-09-14 21:13:50 +00:00
f02994d782
Check that operands have unique names. REJECT instructions with broken operand
...
lists: only don't parse them if they are entirely missing (sparcv9).
llvm-svn: 23355
2005-09-14 21:05:02 +00:00
24ae3494f0
fix a broke range check
...
llvm-svn: 23354
2005-09-14 21:04:12 +00:00
3ba60bf644
Parse significantly more of the instruction pattern, now collecting and
...
verifying information about the operands.
llvm-svn: 23353
2005-09-14 20:53:42 +00:00
22e60c99ce
Verify that set destinations occur first in the instruction operand list.
...
llvm-svn: 23351
2005-09-14 18:19:25 +00:00
fcffc98b05
add an accessor
...
llvm-svn: 23349
2005-09-14 18:02:53 +00:00
1c8d6ce015
remove some code that isn't ready for prime time
...
llvm-svn: 23346
2005-09-14 06:03:10 +00:00
3361eab530
Switch to a slightly more structured representation for instructions
...
llvm-svn: 23345
2005-09-14 04:03:16 +00:00
4cfcb544bf
Add some more checking/verification code
...
llvm-svn: 23344
2005-09-14 02:11:12 +00:00
4c7b604091
start parsing instructions into patterns, start doing many more checks of
...
'set's.
llvm-svn: 23343
2005-09-14 00:09:24 +00:00
bb9b01644e
don't emit the namespace inside the class!
...
llvm-svn: 23341
2005-09-13 22:05:02 +00:00
70a7234111
Emit code suitable for emission into the ISel class, allowing us to use/define
...
methods.
llvm-svn: 23340
2005-09-13 22:03:37 +00:00
3556d849da
continue xform function parsing
...
llvm-svn: 23338
2005-09-13 21:59:15 +00:00
2617de498d
Start parsing node transformation information
...
llvm-svn: 23337
2005-09-13 21:51:00 +00:00
ae939eb6bb
Add a new Record::getValueAsCode method to mirror the other getValueAs*
...
methods. Use it to simplify some code.
llvm-svn: 23336
2005-09-13 21:44:28 +00:00
f365e25a5c
completely eliminate TreePattern::PatternType
...
llvm-svn: 23335
2005-09-13 21:20:49 +00:00
d0c7a5eeb7
Regenerate
...
llvm-svn: 23311
2005-09-12 05:30:06 +00:00
564d240799
Rearrange two rules, which apparently makes some versions of bison happier.
...
llvm-svn: 23310
2005-09-12 05:29:43 +00:00
0dce12dd90
Fix miscellaneous Visual Studio build problems.
...
llvm-svn: 23307
2005-09-10 02:00:02 +00:00
ce2173d098
add an accessor to provide more checking
...
llvm-svn: 23289
2005-09-09 01:15:01 +00:00
7a82c06f34
use new accessors to simplify code. Add checking to make sure top-level instr
...
definitions are void
llvm-svn: 23288
2005-09-09 01:11:44 +00:00
91d8672be1
add some accessors
...
llvm-svn: 23287
2005-09-09 01:11:17 +00:00
debd6e95ab
Fix incorrect comment
...
llvm-svn: 23285
2005-09-08 23:26:30 +00:00
d7d31f3b06
Implement a complete type inference system for dag patterns, based on the
...
constraints defined in the DAG node definitions in the .td files. This
allows us to infer (and check!) the types for all nodes in the current
ppc .td file. For example, instead of:
Inst pattern EQV: (set GPRC:i32:$rT, (xor (xor GPRC:i32:$rA, GPRC:i32:$rB), (imm)<<Predicate_immAllOnes>>))
we now fully infer:
Inst pattern EQV: (set:void GPRC:i32:$rT, (xor:i32 (xor:i32 GPRC:i32:$rA, GPRC:i32:$rB), (imm:i32)<<Predicate_immAllOnes>>))
from: (set GPRC:$rT, (not (xor GPRC:$rA, GPRC:$rB)))
llvm-svn: 23284
2005-09-08 23:22:48 +00:00
cee994b464
Compute the value types that are natively supported by a target.
...
llvm-svn: 23282
2005-09-08 21:43:21 +00:00
1c33104010
Parse information about type constraints on SDNodes
...
llvm-svn: 23281
2005-09-08 21:27:15 +00:00
a3b89dfcef
use node info in the one place we currently use it
...
llvm-svn: 23280
2005-09-08 21:04:46 +00:00
35bcd1488a
start parsing SDNode info records
...
llvm-svn: 23279
2005-09-08 21:03:01 +00:00
07f1e4597e
Fix indentation
...
llvm-svn: 23276
2005-09-08 19:47:28 +00:00
bd6b164965
regenerate
...
llvm-svn: 23275
2005-09-08 18:48:47 +00:00
972cccd77a
Add support for automatically created anonymous definitions.
...
This implements Regression/TableGen/AnonDefinitionOnDemand.td
llvm-svn: 23274
2005-09-08 18:48:23 +00:00
5a699e621f
regenerate
...
llvm-svn: 23271
2005-09-08 18:22:57 +00:00
8a41b214b3
Tabs to spaces.
...
llvm-svn: 23270
2005-09-08 18:22:35 +00:00
399f59f643
Keep names even when inlining. This allows us to realize that ADDI is:
...
(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>:$imm))
not:
(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>))
(we keep the ":$imm")
llvm-svn: 23269
2005-09-08 17:45:12 +00:00
d2a5b366f5
Initial cut of the dag isel generator. This is still very much a work in
...
progress. It correctly parses instructions and pattern fragments and glues
together pattern fragments into instructions.
The only code it generates currently is some boilerplate code for things
like the EntryNode.
llvm-svn: 23261
2005-09-07 23:44:43 +00:00
c59a1dbce2
Rename a class. These files are being migrated to the new isel and I want to
...
reuse the names
llvm-svn: 23252
2005-09-06 22:51:34 +00:00
784e44443d
regenerate
...
llvm-svn: 23249
2005-09-06 21:23:27 +00:00
ab9eba1014
Tighten up the specification to allow TableGen/nested-comment.td to pass
...
(fixing a bug where / in a /* */ comment would cause it to not close).
llvm-svn: 23248
2005-09-06 21:23:09 +00:00
90d000417f
Add an option and stuff implementation of a dag isel emitter
...
llvm-svn: 23236
2005-09-03 01:14:03 +00:00
dfb3fb4a25
Implement PR614:
...
These changes modify the makefiles so that the output of flex and bison are
placed in the SRC directory, not the OBJ directory. It is intended that they
be checked in as any other LLVM source so that platforms without convenient
access to flex/bison can be compiled. From now on, if you change a .y or
.l file you *must* also commit the generated .cpp and .h files.
llvm-svn: 23115
2005-08-27 18:50:39 +00:00
c6a0338c04
spell this right
...
llvm-svn: 23099
2005-08-26 20:55:40 +00:00
63dc7f569a
spell this variable right
...
llvm-svn: 23095
2005-08-26 20:42:52 +00:00
3d9fbefbf7
Expose a new flag to TargetInstrInfo
...
llvm-svn: 23094
2005-08-26 20:40:46 +00:00
c36c9bdb5d
add a marker at the end of the instruction enum list
...
llvm-svn: 23090
2005-08-26 20:17:00 +00:00
96d0234845
Emit this:
...
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };
instead of this:
static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };
For operand information, which does not require dynamic (startup-time)
initialization.
llvm-svn: 22931
2005-08-19 20:29:14 +00:00
8ed3d0a0ce
Expose the derived register classes to the public header, allowing them
...
to be accessed.
llvm-svn: 22930
2005-08-19 20:23:42 +00:00
73ec2cb0f5
Split register class "Methods" into MethodProtos and MethodBodies
...
llvm-svn: 22928
2005-08-19 19:12:51 +00:00
74f60c306d
Refactor to use Target.getRegisterClasses consistently, which provides
...
anonymous regclass definition renaming.
Change the generated code to emit register classes as properly namespace
qualified entities like everything else.
expose the actual class definition as an object, though this isn't quite
usable yet.
llvm-svn: 22920
2005-08-19 18:47:59 +00:00
d02bd5bb05
Emit real operand info for instructions. This currently works but is bad
...
in one way: the generated tables require dynamic initialization for the
register classes. This will be fixed in a future patch.
llvm-svn: 22919
2005-08-19 18:46:26 +00:00
418d8cfcfe
Read the namespace field from register classes
...
llvm-svn: 22918
2005-08-19 18:45:20 +00:00
f9b2edb91f
add a setName method to record
...
llvm-svn: 22912
2005-08-19 17:58:49 +00:00
ac284259ac
Add a setName method to Record.
...
llvm-svn: 22911
2005-08-19 17:58:11 +00:00
220d00109b
For now, just emit empty operand info structures.
...
llvm-svn: 22910
2005-08-19 16:57:28 +00:00
0899614152
Fix a problem jeffc noticed
...
llvm-svn: 22903
2005-08-19 06:16:04 +00:00
04a5ae3f71
The code emitter generator only supports targets with 32-bit instruction
...
words. There is no way for one of these targets to have a > 32-bit immediate!
llvm-svn: 22897
2005-08-19 01:04:33 +00:00
511ee687e5
now that all of the targets are clean w.r.t. the number of operands for each
...
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter
llvm-svn: 22895
2005-08-19 00:59:49 +00:00
17727bad02
Figure out how many operands each instruction has, keep track of whether
...
or not it's variable.
llvm-svn: 22885
2005-08-18 23:38:41 +00:00
b015303c5e
revert this change, which causes breakage, temporarily
...
llvm-svn: 22880
2005-08-18 22:12:31 +00:00
99df668f48
When emitting implicit use/def lists, only emit each unique list once. Though
...
LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data. This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.
This should speed up the register allocator as well by reducing the dcache
footprint for this static data.
llvm-svn: 22879
2005-08-18 21:36:47 +00:00
6f52a04fc7
Fill in the numOperands field of the TargetInstrDescriptor struct from the
...
.td file.
llvm-svn: 22873
2005-08-18 19:45:37 +00:00
5f4ef3c5a8
Eliminate all remaining tabs and trailing spaces.
...
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
3a6a4d3707
Fix PR595: These error messages should not be looking at CGI.Name, they
...
should be looking at CGI.TheDef->getName().
llvm-svn: 22445
2005-07-15 22:43:04 +00:00
4f229d5197
Add support for a TODO; instructions in .td files can now have arguments
...
printed as part of the opcode. This allows something like
cmp${cc}ss in the x86 backed to be printed as cmpltss, cmpless, etc.
depending on what the value of $cc is.
llvm-svn: 22439
2005-07-14 22:50:30 +00:00
88e7b7288a
Eliminate tabs and trailing spaces
...
llvm-svn: 21441
2005-04-22 04:13:13 +00:00
650ba8eb56
Remove trailing whitespace
...
llvm-svn: 21428
2005-04-22 00:00:37 +00:00
14db4a2895
ignore generated files
...
llvm-svn: 21362
2005-04-19 15:34:36 +00:00
b17483028f
fix bogus warning
...
llvm-svn: 21361
2005-04-19 15:32:30 +00:00
ef94374a1c
Major change to tblgen: instead of resolving values every time a class is
...
finished up, only resolve fully when the def is defined. This allows things
to be changed and all uses to be propagated through. This implements
TableGen/LazyChange.td and fixes TemplateArgRename.td in the process.
None of the .td files used in LLVM backends are changed at all by this
patch.
llvm-svn: 21344
2005-04-19 03:36:21 +00:00
3ff0e11294
implementing shifting of literal integers
...
llvm-svn: 21336
2005-04-19 01:17:35 +00:00
101fc501d0
Add initial lexer and parser support for shifting values. Every use of this
...
will lead to it being rejected though.
llvm-svn: 21335
2005-04-19 01:11:03 +00:00
97cf8fd4a9
Minor fix.
...
llvm-svn: 19761
2005-01-22 20:59:38 +00:00
59a7f5c2f3
This is the final big of factoring. This shares cases in suboperand
...
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
llvm-svn: 19760
2005-01-22 20:31:17 +00:00
92275bb6bb
Implement *even more* factoring. In particular, if all of the instruction
...
strings starts out with a constant string, we emit the string first, using
a table lookup (instead of a switch statement).
Because this is usually the opcode portion of the asm string, the differences
between the instructions have now been greatly reduced. This allows many
more case statements to be grouped together.
This patch also allows instruction cases to be grouped together when the
instruction patterns are exactly identical (common after the opcode string
has been ripped off), and when the differing operand is a MachineInstr
operand that needs to be formatted.
The end result of this is a mean and lean generated AsmPrinter!
llvm-svn: 19759
2005-01-22 19:22:23 +00:00
945e8655dd
Refactor code for numbering instructions into CodeGenTarget.
...
llvm-svn: 19758
2005-01-22 18:58:51 +00:00
da636b3783
Fix VC++ compilation error
...
llvm-svn: 19757
2005-01-22 18:50:10 +00:00
9ceb7c8f23
Implement factoring of instruction pattern strings. In particular, instead of
...
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
llvm-svn: 19755
2005-01-22 18:38:13 +00:00
b6f5d9a82a
Fix the ::: problem
...
llvm-svn: 19754
2005-01-22 18:18:59 +00:00
3baf682110
Minor refactoring, no functionality change.
...
llvm-svn: 19753
2005-01-22 17:40:38 +00:00
0c23ba5c0f
Seperate asmstring parsing from emission. This allows the code to be simpler
...
and more understandable. It also allows us to do simple things like fold
consequtive literal strings together. For example, instead of emitting this
for the X86 backend:
O << "adc" << "l" << " ";
we now generate this:
O << "adcl ";
*whoa* :)
This shrinks the X86 asmwriters from 62729->58267 and 65176->58644 bytes
for the intel/att asm writers respectively.
llvm-svn: 19749
2005-01-22 17:32:42 +00:00
67e2e21353
make double-dollar properly escape asmstrings
...
llvm-svn: 19740
2005-01-22 00:35:22 +00:00
733c82bfbf
Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
...
llvm-svn: 19243
2005-01-02 02:29:04 +00:00
1c48c2deee
For PR387:
...
Make this compile without warning when -Woverloaded-virtual is used.
llvm-svn: 18588
2004-12-06 23:42:37 +00:00
b2d0fa0823
Fix usage of changed function prototype
...
llvm-svn: 17798
2004-11-14 22:30:54 +00:00
429aaa5855
Quiet VC++ warnings
...
llvm-svn: 17484
2004-11-05 04:50:59 +00:00
f88808ae43
Internalize variable names to prevent recursive assignment. Cleanup docs.
...
llvm-svn: 17359
2004-10-30 09:19:36 +00:00
57cbe39d1e
Change Library Names Not To Conflict With Others When Installed
...
llvm-svn: 17286
2004-10-27 23:18:45 +00:00
7dfc2d29ac
Convert 'struct' to 'class' in various places to adhere to the coding standards
...
and work better with VC++. Patch contributed by Morten Ofstad!
llvm-svn: 17281
2004-10-27 16:14:51 +00:00
87a1061559
Make VC happier, patch contributed by Morten Ofstad
...
llvm-svn: 17179
2004-10-23 04:58:50 +00:00
5fd95ce095
We're not doing automake any more
...
llvm-svn: 17168
2004-10-22 21:02:23 +00:00
c1c320c335
We won't use automake
...
llvm-svn: 17155
2004-10-22 03:35:04 +00:00
6a11a75f31
Initial automake generated Makefile template
...
llvm-svn: 17136
2004-10-18 23:55:41 +00:00
8393c15b28
* Factor out (into new fn) a loop emitting operand shifts into the instruction
...
* Reverse instruction bit components for a LittleEndian-style encoding
* Fix some comments and spacing
llvm-svn: 16975
2004-10-14 05:53:01 +00:00
243ded5e1a
* Add option to read isLittleEndianEncoding for InstrInfo classes
...
* Doxygen-ify some function comments
llvm-svn: 16974
2004-10-14 05:50:43 +00:00
ac1a547a38
Patch to make VS happier, thanks to Morten Ofstad for pointing this out.
...
llvm-svn: 16956
2004-10-13 15:25:46 +00:00
26bfe011f8
Updates for changes in Makefile rules.
...
llvm-svn: 16951
2004-10-13 11:48:50 +00:00
5499551206
Don't emit the method into the llvm namespace, let the #includer decide where it goes
...
llvm-svn: 16934
2004-10-12 16:21:18 +00:00
b84cbf2725
Initial version of automake Makefile.am file.
...
llvm-svn: 16885
2004-10-10 20:43:57 +00:00
41f9f29996
Properly `quote' names, and don't forget to add the ending quote!
...
llvm-svn: 16838
2004-10-08 14:59:05 +00:00
72770f5877
Correctly parse variant notation
...
llvm-svn: 16637
2004-10-03 20:19:02 +00:00
91c538f2a1
Add initial support for variants. This just parses the new format, no
...
functionality is added
llvm-svn: 16636
2004-10-03 19:34:31 +00:00
46cee7da73
#include DataTypes.h to compile on MinGW, patch by Henrik Bach.
...
llvm-svn: 16616
2004-09-30 18:27:39 +00:00
996ddbc98e
Add support for the isLoad and isStore flags, needed by the instruction scheduler
...
llvm-svn: 16554
2004-09-28 21:01:45 +00:00
9b0dfa3c0d
Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
...
llvm-svn: 16553
2004-09-28 18:38:01 +00:00
e8e81a2941
Revamp the Register class, and allow the use of the RegisterGroup class to
...
specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
llvm-svn: 16330
2004-09-14 04:17:02 +00:00
0ded30aec4
Clean up some "clean:" targets so they use $(VERB) and don't print anything
...
by default, like every other "clean" target in LLVM.
llvm-svn: 16161
2004-09-03 23:19:53 +00:00
c8ec13388b
Make tblgen's exception handling a little more robust by printing the
...
program name and also catching ...
llvm-svn: 16160
2004-09-03 23:17:54 +00:00
7c16caa336
Changes For Bug 352
...
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
811c3c0edb
Link with LLVMsystem.a for operating system independence.
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llvm-svn: 16094
2004-08-29 19:31:19 +00:00
9b129bea2e
RemoveFileOnErrorSignal is now in the llvm::sys namespace. Adjust
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accordingly.
llvm-svn: 16093
2004-08-29 19:30:41 +00:00
8eab62ee0d
Alignment is now in bits.
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llvm-svn: 15976
2004-08-21 20:15:25 +00:00
beadefde19
Make alignment be in bits, just like size is
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llvm-svn: 15969
2004-08-21 20:00:36 +00:00
a6d34d9e19
Infer the spillsize/alignment of a register based on the register classes
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it is embedded into.
llvm-svn: 15966
2004-08-21 19:42:03 +00:00
d3244d9cec
Support "Methods" in register classes in CodgeGenRegisterClass
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llvm-svn: 15965
2004-08-21 19:21:21 +00:00
2a86fab933
Start parsing register classes into a more structured form
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llvm-svn: 15961
2004-08-21 04:05:00 +00:00
e34ae99942
Read in declared reg sizes
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llvm-svn: 15960
2004-08-21 02:24:57 +00:00
c9d99efdd3
Do not #include files into the llvm namespace
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llvm-svn: 15849
2004-08-17 03:08:28 +00:00
8af61ddb96
Use CodeGenRegister class to make reading in of register information more
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systematic.
llvm-svn: 15805
2004-08-16 01:10:21 +00:00
b7b70480e1
Add initial support for register and register class representation.
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Obviously this is not done.
llvm-svn: 15804
2004-08-16 01:09:52 +00:00
0bbf7005f5
Remove awareness of isDummyClass
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llvm-svn: 15789
2004-08-15 23:04:13 +00:00
6ffa501d9f
Make the AsmWriter a first-class tblgen object. Allow targets to specify
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name of the generated asmwriter class, and the name of the format string.
llvm-svn: 15747
2004-08-14 22:50:53 +00:00
baa2ecb798
Fix minor bug in previous checkin
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llvm-svn: 15649
2004-08-11 04:08:36 +00:00
c1904dd38f
change how we invoke the printer. Instead of passing in the MO directly,
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pass in the MI, operand number, and the type of the operand.
llvm-svn: 15645
2004-08-11 02:23:23 +00:00
3bc477a237
Start parsing more information from the Operand information
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llvm-svn: 15644
2004-08-11 02:22:39 +00:00
101f3fea82
Remove special case hacks
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llvm-svn: 15643
2004-08-11 01:53:58 +00:00
422d0fadf1
Deleted commented-out code as we now get namespace directly, add comments
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llvm-svn: 15627
2004-08-10 20:54:58 +00:00
59978333a3
Use the target name instead of hard-coding SparcV9.
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llvm-svn: 15616
2004-08-10 18:31:01 +00:00
79db057a3b
This was a good idea, but until this does not break the build of
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lib/Target/Sparc, we should not use it.
llvm-svn: 15603
2004-08-10 15:05:18 +00:00
920ae9524d
Use the current target name instead of a ClassPrefix.
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llvm-svn: 15585
2004-08-09 19:10:43 +00:00
18d27dc342
* Use Classname and ClassPrefix instead of hard-coded V9 values
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* Simplify code and shorten lines by not recomputing values
llvm-svn: 15582
2004-08-09 17:47:45 +00:00
Evan Cheng